Patents in Class 365/156

Matches 1 - 50 out of 714

Match	Document	Document Title
1	7626850	Systems and devices for implementing sub-threshold memory devices Various systems and methods for implementing memory devices are disclosed. For example, some embodiments of the present invention provide sub-threshold memory devices that include a differential...
2	7626853	Method of operating memory cell providing internal power switching Various implementations are provided that may be used to improve the writeability of individual memory cells providing internal power switching. For example, in one implementation, a method is...
3	7626855	Semiconductor memory device Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS...
4	7619947	Integrated circuit having a supply voltage controller capable of floating a variable supply voltage An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply...
5	7619916	8-T SRAM cell circuit, system and method for low leakage current An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored...
6	7613054	SRAM device with enhanced read/write operations An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells...
7	7613030	Semiconductor memory device and method for operating the same A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically...
8	7613050	Sense-amplifier assist (SAA) with power-reduction technique A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA)...
9	7606060	Eight transistor SRAM cell with improved stability requiring only one word line An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right...
10	7605447	Highly manufacturable SRAM cells in substrates with hybrid crystal orientation The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down...
11	7602635	Structure for a configurable SRAM system and method A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In...
12	7599214	Semiconductor memory device Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and...
13	7598544	Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube...
14	7596040	Methods and apparatus for improved write characteristics in a low voltage SRAM Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and...
15	7596013	Semiconductor integrated circuit and manufacturing method therefor High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each...
16	7593252	Semiconductor apparatus having shield line provided between internal layer and input/output line in layout cell A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors...
17	7583526	Random access memory including nanotube switching elements Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes...
18	7573775	Setting threshold voltages of cells in a memory block to reduce leakage in the memory block In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and...
19	7570509	Semiconductor device, logic circuit and electronic equipment A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first...
20	7558112	SRAM cell controlled by flash memory cell First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first...
21	7558104	Power saving in memory arrays An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input...
22	7545670	Dual word line or floating bit line low power SRAM Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and...
23	7542333	Logic cell protected against random events A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second...
24	7542330	SRAM with asymmetrical pass gates An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain...
25	7542334	Bistable latch circuit implemented with nanotube-based switching elements A nanotube-based switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in...
26	7542368	Semiconductor memory device A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is...
27	7539931	Storage element for mitigating soft errors in logic In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output...
28	7535750	Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells Asymmetrical random access memory cell ( 1 ) including cross coupled inverters ( 2, 3 ) which are driven at their nodes ( 22, 32 ) by separate bit-lines (blt, blc) of a pair of complementary...
29	7535782	Sense amplifier circuit and method for a DRAM A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of...
30	7532536	Semiconductor memory device The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control...
31	7529118	Generalized interlocked register cell (GICE) A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels...
32	7525835	Method and apparatus for reduced power cell The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an...
33	7525836	Non-imprinting memory with high speed erase A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive...
34	7515452	Interleaved memory cell with single-event-upset tolerance A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the...
35	7515489	SRAM having active write assist for improved operational margins A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a...
36	7505304	Fault tolerant asynchronous circuits New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event...
37	7498637	Semiconductor memory A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor...
38	7492628	Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell Techniques are provided for a computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed...
39	7492627	Memory with increased write margin bitcells A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply...
40	7489540	Bitcell with variable-conductance transfer gate and method thereof A memory device comprises a bit cell comprising a bit storage device, a first word line, a second word line, and a first transfer gate to connect the bit storage device to a bit line. The first...
41	7486544	Semiconductor integrated circuit device The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a...
42	7486543	Asymmetrical SRAM device and method of manufacturing the same In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a...
43	7486541	Resistive cell structure for reducing soft error rate A memory cell for reducing soft error rate and the method for forming same are disclosed. The memory cell comprises a first bit line signal (BL), a second bit line signal complementary to the first...
44	7480169	Ideal CMOS SRAM system implementation CMOS static RAM based memory system, which reduces power consumption and increases operation speed by disconnecting cell power supply during write operation. Additional transistors are provided...
45	7480192	Pull-up voltage circuit A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor...
46	7477566	Multi-port semiconductor memory A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit...
47	7474553	Device writing to a plurality of rows in a memory matrix simultaneously A word line driver circuit ( 10 ) is coupled to word lines ( 18 ) of a memory matrix, for example a matrix of content addressable cells ( 12 ). The word line driver circuit is capable of selecting...
48	7471548	Structure of static random access memory with stress engineering for stability An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability....
49	7471546	Hierarchical six-transistor SRAM An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are...
50	7466604	SRAM voltage control for improved operational margins A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control...

Matches 1 - 50 out of 714

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