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7606060 Eight transistor SRAM cell with improved stability requiring only one word line  
An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right...
7596013 Semiconductor integrated circuit and manufacturing method therefor  
High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each...
7532539 Semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to load  
A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor...
7492628 Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell  
Techniques are provided for a computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed...
7443717 Semiconductor device  
A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory...
7443715 SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators  
Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide...
7362606 Asymmetrical memory cells and memories using the cells  
Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first...
7313012 Back-gate controlled asymmetrical memory cell and memory using the cell  
Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM)...
7295458 Eight transistor SRAM cell with improved stability requiring only one word line  
An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right...
7242607 Diode-based memory including floating-plate capacitor and its applications  
Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third...
7139190 Single event upset tolerant memory cell layout  
Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells...
6914804 Memory cells enhanced for resistance to single event upset  
Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch,...
6859387 Three-state binary adders and methods of operating the same  
Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital...
6271568 Voltage controlled resistance modulation for single event upset immunity  
An SRAM cell includes six transistors and two variable resistors. A first pair of transistors form a first inverter, while a second pair of transistors form a second inverter. The remaining two...
6096496 Supports incorporating vertical cavity emitting lasers and tracking apparatus for use in combinatorial synthesis  
A combinatorial chemistry bead that includes an electromagnetic spectral emitter that radiates a distinct electromagnetic code for each bead that uniquely identifies each bead, a terminal apparatus...
6088259 SRAM cell using two single transistor inverters  
A SRAM cell is disclosed. The SRAM cell comprises: a first inverter having an input and an output; a second inverter having an input and an output, the output of the second inverter capacitively...
5966324 Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells  
Memory cells which are adjacent to each other along a column direction share a bipolar transistor driving the potential level of a corresponding bit line. Other memory cells which are adjacent to...
5383153 Semiconductor memory device with flash-clear function  
A semiconductor memory device equipped with a flash-clear function has a plurality of flip-flop type memory cells each of which is formed by a first multi-emitter transistor and a second...
5289409 Bipolar transistor memory cell and method  
Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied...
5276638 Bipolar memory cell with isolated PNP load  
A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is...
5216630 Static semiconductor memory device using bipolar transistor  
Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The...
5200924 Bit line discharge and sense circuit  
A bit line discharge and sense circuit is provided for use with a static RAM that includes a row and column array of memory cells addressable via first and second bit lines and also a row select...
5140399 Heterojunction bipolar transistor and the manufacturing method thereof  
A heterojunction bipolar transistor formed as a collector top or emitter top type. This heterojunction bipolar transistor can operate at high speed and can be fabricated into a semiconductor...
5117390 Semiconductor memory system for use in logic LSI's  
A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor...
5117391 Bipolar memory cell array biasing technique with forward active PNP load cell  
A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through...
5091881 Multiple port memory including merged bipolar transistors  
A multiple port memory includes memory cells with merged PNP and NPN bipolar transistors. Each memory cell has a pair of PNP load transistors and a pair of NPN control transistors in a symmetric...
5083292 Bipolar random access memory  
A bipolar random access memory comprises a plurality of memory cells arranged in row and column formation, a plurality of word lines provided in correspondence to respective rows of the memory...
5043939 Soft error immune memory  
An alpha radiation immune integrated circuit memory cell has a pair of secondary transistors connected to cross-couple the primary transistors to form a flow, secondary storage node. The secondary...
5029129 High-speed bipolar memory system  
A switched load diode cell has been developed wherein first and second multi-emitter NPN transistors are provided having bases cross coupled to the other's collectors in typical latch fashion as...
5029127 Bipolar SRAM having word lines as vertically stacked pairs of conductive lines parallelly formed with holding current lines  
There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a...
5016214 Memory cell with separate read and write paths and clamping transistors  
Two pairs of bit lines are associated with each column of memory cells in a static random access memory (RAM) to provide separate paths for reading and writing operations or to provide a RAM having...
4956688 Radiation resistant bipolar memory  
A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are...
4922411 Memory cell circuit with supplemental current  
A memory cell circuit with a pair of load bipolar transistors and a pair of control bipolar transistors, and with a pair of supplemental transistors providing current shunts.
4899311 Clamping sense amplifier for bipolar ram  
A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has...
4868904 Complementary noise-immune logic  
Logic gates with large logic swings and large noise margins use complementary pull-up and pull-down enhancement-mode drivers. Connected between the input node of the logic gate and the control...
4864540 Bipolar ram having no write recovery time  
A bipolar random access memory having no write recovery time. During a data write operation, while the memory state of the memory cell is being shifted, a data bypass circuit sets a sense latch in...
4864539 Radiation hardened bipolar static RAM cell  
This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to α-particle radiation is reduced by permitting...
4858181 Fast recovery PNP loaded bipolar static RAM memory cell with an independent current path  
A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an...
4853898 Bipolar ram having state dependent write current  
A bipolar RAM having improved read and write cycle times. During a write operation, the state of a selected memory cell is sensed by read/write current controller circuits. A high write current is...
4823315 Plural emitter memory with voltage clamping plural emitter transistor  
A transistor memory cell device comprising a pair of cross-coupled transistors constituting storage elements for storing binary information and having column drive emitter inputs to which a...
4809052 Semiconductor memory device  
A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least...
4805149 Digital memory with reset/preset capabilities  
A digital memory characterized by a plurality of memory cells arranged into a matrix having rows and columns; a row activation circuit for concurrently activating all of the rows of the matrix; and...
4792923 Bipolar semiconductor memory device with double word lines structure  
A semiconductor memory device having a plurality of word line pairs and drain lines, a plurality of bit line pairs, and a plurality of memory cells connected to both of the word line pairs and the...
4783765 Bipolar memory cell with cross-connected transistors and an external capacitance  
An integrated bipolar memory cell with random access, includes an upper word line, a lower word line, two bit lines, two transistors each having two emitters, a base and a collector fed back...
4769785 Writing speed of SCR-based memory cells  
Load resistors are connected in series between the PNP portions of the SCRs and the upper word-line. The load presented to the NPN portions of the SCRs is thus a composite formed of a PNP...
4754430 Memory cell with dual collector, active load transistors  
A memory cell includes two active load, pnp transistors, and two npn switching transistors. The collector and base regions of the switching transistors are cross coupled. Each of the load...
4745580 Variable clamped memory cell  
An improved memory cell circuit in which the collector of the "ON" transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for...
4730275 Circuit for reducing the row select voltage swing in a memory array  
A circuit reduces the row select voltage swing in a memory array, thereby reducing access time, power dissipation, disturb problems, glitches on the output, and alpha particle sensitivity. A row...
4697104 Two stage decoder circuit using threshold logic to decode high-order bits and diode-matrix logic to decode low-order bits  
A two-stage decoder circuit includes a first-stage decoder circuit, for decoding upper bits of an input signal, and a second-stage decoder circuit, which is activated by receiving a selected output...
4677455 Semiconductor memory device  
In a semiconductor memory cell having PNPN type memory cells, a vertical PNPN element is used as a load transistor and a sense transistor or a hold transistor, or both. A buried layer is used as a...
Matches 1 - 50 out of 143 1 2 3 >