Patents in Class 365/154

Matches 1 - 50 out of 1760

Match	Document	Document Title
1	7619916	8-T SRAM cell circuit, system and method for low leakage current An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored...
2	7616516	Semiconductor device A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit...
3	7613067	Soft error robust static random access memory cells A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell includes the following elements. First and second storage nodes are...
4	7613050	Sense-amplifier assist (SAA) with power-reduction technique A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA)...
5	7613032	Semiconductor memory device and control method thereof A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter...
6	7613031	System, apparatus, and method to increase read and write stability of scaled SRAM memory cells Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably...
7	7613030	Semiconductor memory device and method for operating the same A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically...
8	7609542	Implementing enhanced SRAM read performance sort ring oscillator (PSRO) A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject...
9	7609541	Memory cells with lower power consumption during a write operation A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further...
10	7606108	Access collision within a multiport memory A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access...
11	7606062	Ultra low voltage and minimum operating voltage tolerant register file Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes...
12	7606061	SRAM device with a power saving module controlled by word line signals An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a...
13	7606060	Eight transistor SRAM cell with improved stability requiring only one word line An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right...
14	7603510	Semiconductor device and storage cell having multiple latch circuits A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from...
15	7602641	Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass...
16	7602635	Structure for a configurable SRAM system and method A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In...
17	7599232	Semiconductor memory device A word line driving circuit includes first, second, and third MOS transistors. Gates of the first and second transistors are commonly connected. Sources of the first and second transistors are...
18	7599214	Semiconductor memory device Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and...
19	7599210	Nonvolatile memory cell, storage device and nonvolatile logic circuit One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other...
20	7598544	Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube...
21	7596013	Semiconductor integrated circuit and manufacturing method therefor High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each...
22	7596012	Write-assist and power-down circuit for low power SRAM applications Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an...
23	7593276	Semiconductor memory device A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier...
24	7593252	Semiconductor apparatus having shield line provided between internal layer and input/output line in layout cell A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors...
25	7592836	Multi-write memory circuit with multiple data inputs Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a first data input and to a second data input. The first data input is...
26	7589993	Semiconductor memory device with memory cells operated by boosted voltage A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the...
27	7589992	Semiconductor device having three dimensional structure A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor...
28	7589991	Semiconductor memory device A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs...
29	7586780	Semiconductor memory device In a semiconductor memory device including memory cells each having two inverters connected in a cross-coupled configuration to hold High data and Low data as a pair and two access transistors, a...
30	7583549	Memory output circuit and method thereof An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a...
31	7583526	Random access memory including nanotube switching elements Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes...
32	7580317	Semiconductor memory device A semiconductor memory circuit includes first and second bit lines making a first pair, third and fourth bit lines making a second pair, a memory cell having a first inverter coupled between the...
33	7580305	Semiconductor memory A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each...
34	7577051	SRAM including reduced swing amplifiers SRAM includes reduced swing amplifiers, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing...
35	7577015	Memory content inverting to minimize NTBI effects In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined...
36	7577014	Semiconductor memory device A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory...
37	7577013	Storage units and register file using the same A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a...
38	7573735	Systems and methods for improving memory reliability Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells...
39	7570540	Multiport semiconductor memory device In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is...
40	7570537	Memory cells with power switch circuit for improved low voltage operation Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices....
41	7570533	Completely transportable erasable memory apparatus and method The present invention relates to methods and apparatuses for providing data storage which can be completely erased to prevent access to previously stored data.
42	7570527	Static random-access memory having reduced bit line precharge voltage and method of operating the same A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word...
43	7570525	Semiconductor memory device with adjustable selected work line potential under low voltage condition A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line....
44	7570509	Semiconductor device, logic circuit and electronic equipment A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first...
45	7570508	Method and apparatus for reducing soft errors A method and apparatus for reducing soft errors in which the method includes: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals...
46	7570503	Ternary content addressable memory (TCAM) cells with low signal line numbers A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data...
47	7561483	Internally asymmetric method for evaluating static memory cell dynamic stability An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the...
48	7561480	Ground biased bitline register file In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is...
49	7561454	Compare circuit for a content addressable memory cell A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of...
50	7560956	Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether...

Matches 1 - 50 out of 1760

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