Matches 301 - 350 out of 1776 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7304895 Bitline variable methods and circuits for evaluating static memory cell dynamic stability  
Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering...
7304874 Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas  
Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of...
7304884 Semiconductor memory device  
A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and...
7304908 SRAM device capable of performing burst operation  
Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single...
7304352 Alignment insensitive D-cache cell  
A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell...
7301797 Method of operating semiconductor integrated circuit including SRAM block and semiconductor integrated circuit including SRAM block  
A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile...
7301798 Random access memory cell of reduced size and complexity  
A memory cell ( 1 ), includes a flip-flop ( 2 ) that has additional read/write terminals; a 1-bit write line (wb 11 ); a first transistor (T 4 ) switching between the 1-bit write line and the...
7298641 Configurable storage device  
An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at...
7298659 Method and system for accelerated detection of weak bits in an SRAM memory device  
A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory...
7295458 Eight transistor SRAM cell with improved stability requiring only one word line  
An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right...
7295459 Static random access memory (SRAM) cell  
An SRAM memory cell employing thin-film transistors is provided having a first transmission gate, a second transmission gate and a bi-stable flip-flop comprising a first and a second inverter...
7292486 Methods and circuits for latency control in accessing memory devices  
Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in...
7292485 SRAM having variable power supply and method therefor  
A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled...
7292492 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device  
An SRAM (Static Ransom Access Memory) has a refreshing unit for performing a refreshing operation to maintain a state of an electric charge in a memory cell in order to prevent stored data from...
7289355 Pre-written volatile memory cell  
A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters ( 20 and 21 ) configured as a flip-flop for...
7288960 Sharing a static random-access memory (SRAM) table between two or more lookup tables (LUTs) that are equivalent to each other  
In one embodiment, a system for sharing a static random-access memory (SRAM) table between two or more lookup tables (LUTs) that are equivalent to each other includes at least two basic logic...
7286438 Dual port memory cell with reduced coupling capacitance and small cell size  
A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are...
7286389 Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells  
Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells are disclosed. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch...
7286390 Memory cell and semiconductor integrated circuit device  
A memory cell includes a memory cell section and a switching section. The memory cell section includes first and second inverters which are connected to form a flip-flop, and each of the first and...
7286382 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability  
A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between...
7283411 Flood mode implementation for continuous bitline local evaluation circuit  
A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used...
7280387 SRAM cell comprising a reference transistor for neutralizing leakage current and associated read and write method  
A memory cell comprises a first inverter (IA) and a second inverter (IB) coupled upside down to each other between a first node (A) and a second node (B), and a first access transistor (TA) having...
7281094 Balanced bitcell for a multi-port register file  
In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first...
7279755 SRAM cell with improved layout designs  
A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second...
7280378 CAM cells and CAM matrix made up of a network of such memory cells  
A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of...
7280397 Three-dimensional non-volatile SRAM incorporating thin-film device layer  
A shadow RAM or “non-volatile SRAM” memory cell is implemented in a much smaller area by building the cell upward rather than outward. By stacking non-volatile storage devices above or below an...
7274589 Semiconductor storage device  
An SRAM cell 1 includes inverters 10, 20 , N-type FETs 32, 34, 36, 38 , word lines 42, 44 , bit lines 46, 48 , and voltage applying circuits 50, 60 . The voltage applying circuits 50, 60 ...
7274072 Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance  
The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or...
7274590 Random access memory with stability enhancement and early read elimination  
A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the...
7272071 Systems and methods that employ inductive current steering for digital logic circuits  
The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional...
7272029 Transition-encoder sense amplifier  
A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit...
7272030 Global bit line restore timing scheme and circuit  
A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This...
7269057 Method for connecting circuit elements within an integrated circuit for reducing single-event upsets  
A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are...
7269056 Power grid design for split-word line style memory cell  
Disclosed is an improved power grid design for split-word line style memory cell. An array of memory cells comprises a first metal layer for local interconnections; a second metal layer for a bit...
7269055 SRAM device with reduced leakage current  
The present invention discloses a memory device with a leakage current reduction feature. The memory device includes at least one memory cell for storing a value, and at least one switch module...
7266010 Compact static memory cell with non-volatile storage capability  
A static random access memory (SRAM) cell includes a SRAM circuit and a programmable resistor connected to a storage node of the SRAM circuit. The SRAM circuit can be any type of SRAM circuit, such...
7266035 Self-aligned row-by-row dynamic VDD SRAM  
A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells...
7262987 SRAM cell using tunnel current loading devices  
An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read...
7262988 Memory device and semiconductor device  
A memory circuit includes a latch circuit having a first inverter and a second inverter, a first ferroelectric capacitor that gives a first capacitance to a power supply terminal of the first...
7259977 Semiconductor device having hierarchized bit lines  
A semiconductor device having hierarchized bit lines including an upper-layer bit line and a lower-layer bit line, includes at least one memory cell array to which the lower-layer bit line is...
7257017 SRAM cell for soft-error rate reduction and cell stability improvement  
An SRAM device includes a memory cell. The memory cell includes a first cross-coupled inverter and a second cross-coupled inverter, which is electrically connected to the first cross-coupled...
7254085 Static random access memory device and method of reducing standby current  
A semiconductor storage device includes first and second additional FETs disposed in parallel on one of potential lines for supplying first and second drive potentials to each SRAM memory cell. The...
7251150 Radiation-hardened programmable device  
A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having...
7251175 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme  
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method...
7251183 Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit  
A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the...
7248508 Data retention in a semiconductor memory  
The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching...
7248519 Semiconductor device that initializes memory cells of an activated wordline group  
A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control...
7248523 Static random access memory (SRAM) with replica cells and a dummy cell  
A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes...
7245520 Random access memory including nanotube switching elements  
A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a...
7242626 Method and apparatus for low voltage write in a static random access memory  
An integrated circuit memory includes a plurality of memory cells, where each of the plurality of memory cells comprises a first storage node and a second storage node. Each of the plurality of...
Matches 301 - 350 out of 1776 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >