Matches 251 - 300 out of 1776 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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7359232 Multi-context memory cell  
The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored...
7359266 Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same  
Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and...
7355880 Soft error resistant memory cell and method of manufacture  
A semiconductor device memory cell ( 100 ) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell ( 100 ) can include a first inverter ( 102 ) and second inverter (...
7355881 Memory array with global bitline domino read/write scheme  
A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit...
7352609 Voltage controlled static random access memory  
A static random access memory (SRAM) ( 200, 400 ) comprising a plurality of SRAM cells ( 204 ), a plurality of wordlines (WL 0 -WLN) and a voltage regulator ( 240, 240′, 300, 516 ) for driving...
7352611 Semiconductor integrated circuit  
Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source...
7352610 Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits  
Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal...
7349271 Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance  
A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A...
7349241 SRAM circuitry  
A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell...
7349240 Semiconductor memory device having reduced leakage current  
A static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply...
7345909 Low-power SRAM memory cell  
An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read...
7345910 Semiconductor device  
The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory...
7342821 Hot-carrier-based nonvolatile memory utilizing differing transistor structures  
A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable...
7339845 Memory device  
A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by...
7339850 Semiconductor memory device allowing high-speed data reading  
Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an...
7339816 Soft error tolerance for configuration memory in programmable devices  
A memory device provides improved tolerance against soft errors. A guardian memory cell is connected with a single memory cell or multiple memory cells, which may be unrelated or associated with a...
7336533 Electronic device and method for operating a memory circuit  
An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during...
7336525 Nonvolatile memory for logic circuits  
A memory circuit that retains stored data upon power down includes a volatile data storage circuit; and at least one nonvolatile memory coupled within the volatile data storage circuit, wherein the...
7336542 Nonvolatile latch  
A nonvolatile latch includes a memory element for storing an input data value. A write protect element is coupled to the memory element for utilizing a write protect signal to ensure the input data...
7336546 Global bit select circuit with dual read and write bit line pairs  
A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
7333358 Memory element  
A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of...
7333385 Semiconductor memory device having the operating voltage of the memory cell controlled  
An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the...
7333380 SRAM memory device with flash clear and corresponding flash clear method  
A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS...
7330392 Dual port semiconductor memory device  
A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two...
7327630 Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage  
A power (voltage) switching circuit in a semiconductor memory device, capable of reducing leakage current in a standby mode of operation and shortening the wake-up time when a standby mode is...
7327598 High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode  
An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells...
7327599 Semiconductor memory device  
Included are first and second inverters 1 L, 1 R, a first selection transistor N 1 controlling a connection of an output terminal of the first inverter 1 L to a bit line 11 , and a second...
7327597 Static random access memory architecture  
An architecture for a semiconductor static random access memory (SRAM) is described. In one example, a first set or group or stage of SRAM banks are coupled to a first data bus formed using bit...
7324368 Integrated circuit memory with write assist  
An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4 . The power supply control circuit includes a first gate 26 and a...
7324391 Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback  
A method ( 200 ) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine...
7321506 Multivibrator protected against current or voltage spikes  
The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected...
7321504 Static random access memory cell  
A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is...
7321505 Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect  
A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a...
7319632 Pseudo-dual port memory having a clock for each port  
A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto...
7319603 Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells  
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel...
7315466 Semiconductor memory device and method for arranging and manufacturing the same  
A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor...
7313012 Back-gate controlled asymmetrical memory cell and memory using the cell  
Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM)...
7313021 Nonvolatile memory circuit  
A nonvolatile memory circuit includes a flip-flop to degrade an internal circuit irreversibly based on a voltage applied to a first or second bit line so as to latch data in a nonvolatile manner, a...
7313039 Method for analyzing defect of SRAM cell  
Disclosed is a method for analyzing a defect of a semiconductor device, and more particularly a method for electrically analyzing a defect of a transistor formed in a cell having a latch structure,...
7310281 Semiconductor memories with refreshing cycles  
The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing...
7307905 Low leakage asymmetric SRAM cell devices  
Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM...
7307899 Reducing power consumption in integrated circuits  
A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep”...
7307891 Fast memory circuits and methods  
A storage circuit using a dual-access memory includes means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of...
7307907 SRAM device and a method of operating the same to reduce leakage current during a sleep mode  
An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column...
7307457 Apparatus for implementing dynamic data path with interlocked keeper and restore devices  
A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during...
7307871 SRAM cell design with high resistor CMOS gate structure for soft error rate improvement  
A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The...
7307860 Static content addressable memory cell  
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled...
7307873 Memory with five-transistor bit cells and associated control circuit  
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory...
7307872 Nonvolatile semiconductor static random access memory device  
A nonvolatile semiconductor memory device obtained by combining a nonvolatile memory device with a SRAM is provided to improve operating speed and reliability. The nonvolatile semiconductor memory...
7307861 Content addressable memory (CAM) cell bit line architecture  
A ternary content addressable memory (TCAM) cell ( 100 ) can include two memory elements ( 102 - 0 and 102 - 1 ) with a single bit line ( 106 - 0 and 106 - 1 ) per memory element. A TCAM cell (...
Matches 251 - 300 out of 1776 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >