Patents in Class 365/154

Matches 51 - 100 out of 1777

Match	Document	Document Title
51	7577015	Memory content inverting to minimize NTBI effects In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined...
52	7577014	Semiconductor memory device A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory...
53	7577051	SRAM including reduced swing amplifiers SRAM includes reduced swing amplifiers, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing...
54	7577013	Storage units and register file using the same A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a...
55	7573735	Systems and methods for improving memory reliability Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells...
56	7570540	Multiport semiconductor memory device In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is...
57	7570503	Ternary content addressable memory (TCAM) cells with low signal line numbers A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data...
58	7570533	Completely transportable erasable memory apparatus and method The present invention relates to methods and apparatuses for providing data storage which can be completely erased to prevent access to previously stored data.
59	7570527	Static random-access memory having reduced bit line precharge voltage and method of operating the same A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word...
60	7570525	Semiconductor memory device with adjustable selected work line potential under low voltage condition A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line....
61	7570537	Memory cells with power switch circuit for improved low voltage operation Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices....
62	7570509	Semiconductor device, logic circuit and electronic equipment A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first...
63	7570508	Method and apparatus for reducing soft errors A method and apparatus for reducing soft errors in which the method includes: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals...
64	7561483	Internally asymmetric method for evaluating static memory cell dynamic stability An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the...
65	7561480	Ground biased bitline register file In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is...
66	7560956	Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether...
67	7561454	Compare circuit for a content addressable memory cell A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of...
68	7558140	Method for using a spatially distributed amplifier circuit An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier...
69	7558145	Word line control for improving read and write margins Apparatus to apply a voltage to the word line during a first time interval portion of the access cycle and to apply a further voltage to the word line during a further time interval portion of the...
70	7558097	Memory having bit line with resistor(s) between memory cells For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit...
71	7558112	SRAM cell controlled by flash memory cell First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first...
72	7558104	Power saving in memory arrays An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input...
73	7558136	Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell...
74	7554860	Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first...
75	7554841	Circuit for storing information in an integrated circuit and method therefor A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the...
76	7551475	Data shifting through scan registers A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as...
77	7545690	Method for evaluating memory cell performance A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set...
78	7545671	Static random access memory cell with improved stability A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell...
79	7545670	Dual word line or floating bit line low power SRAM Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and...
80	7542332	Stacked SRAM including segment read circuit Bit lines in SRAM array are multi-divided, so that a segment read circuit is connected to local bit line, which circuit serves as amplifying transistor of an amplifier with load device of a block...
81	7542330	SRAM with asymmetrical pass gates An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain...
82	7542334	Bistable latch circuit implemented with nanotube-based switching elements A nanotube-based switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in...
83	7542329	Virtual power rails for integrated circuits Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits,...
84	7542331	Planar SRAM including segment read circuit Bit lines in SRAM array are multi-divided, so that a segment read circuit is connected to local bit line, which circuit serves as amplifying transistor of an amplifier with load device of a block...
85	7542368	Semiconductor memory device A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is...
86	7539931	Storage element for mitigating soft errors in logic In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output...
87	7535750	Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells Asymmetrical random access memory cell ( 1 ) including cross coupled inverters ( 2, 3 ) which are driven at their nodes ( 22, 32 ) by separate bit-lines (blt, blc) of a pair of complementary...
88	7535782	Sense amplifier circuit and method for a DRAM A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of...
89	7535752	Semiconductor static random access memory device According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor, a first N-channel MOS...
90	7535749	Dynamic memory word line driver scheme A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word...
91	7535743	SRAM memory cell protected against current or voltage spikes A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes....
92	7535751	Dual-port SRAM device A dual-port SRAM cell structure includes a first inverter area where a first inverter is constructed on a semiconductor substrate; a second inverter area where a second inverter is constructed on...
93	7535753	Semiconductor memory device A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and...
94	7535776	Circuit for improved SRAM write around with reduced read access penalty A method for passing data from an input to an output of a domino read access path in domino read SRAM memory including receiving at least a portion of the input data from a latch configuration,...
95	7532501	Semiconductor device including back-gated transistors and method of fabricating the device A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect...
96	7532536	Semiconductor memory device The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control...
97	7529118	Generalized interlocked register cell (GICE) A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels...
98	7529117	Design solutions for integrated circuits with triple gate oxides An integrated circuit includes a first core circuit and a second core circuits. The first core circuit includes a first MOS device, wherein a first gate dielectric of the first MOS device has a...
99	7525854	Memory output circuit and method thereof An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a...
100	7525834	SRAM cell structure and circuits An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as...

Matches 51 - 100 out of 1777

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