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6639826 Memory cell operation using ramped wordlines  
The standby power consumption of storage or memory cells is improved by ramping the wordline voltage down at a rate slow enough to allow the addressed storage cell to reach a more stable voltage...
6639827 Low standby power using shadow storage  
An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored...
6628540 Bias cell for four transistor (4T) SRAM operation  
Quiescent current drawn by an array of four-transistor loadless static random access memory (SRAM) cells is minimized by using a negative feedback loop to set a reference voltage, for the wordline...
6628541 Memory architecture with refresh and sense amplifiers  
An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.
6628539 Multi-entry register cell  
A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to...
6621728 Method of writing a four-transistor memory cell array  
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an...
6621727 Three-transistor SRAM device  
A three-transistor SRAM device are disclosed. The SRAM device has an NMOS with its source connected to a first voltage source and its substrate connected to a second voltage source. The source of...
6614680 Current leakage reduction for loaded bit-lines in on-chip memory structures  
Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or...
6614701 Weak bit testing  
Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective...
6611451 Memory array and wordline driver supply voltage differential in standby  
An SRAM array 22 , with improved leakage in standby, raises the wordline driver lower supply voltage Vss-WL when raising the array lower supply voltage Vss-array in standby. When the SRAM array ...
6608775 Register file scheme  
A circuit including a plurality of latches including feedback control circuitry and a plurality of data input terminals and data output terminals respectively coupled to alternative sides of said...
6608788 Bitline precharge  
An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according...
6597629 Built-in precision shutdown apparatus for effectuating self-referenced access timing scheme  
Self-referenced, built-in access shutdown mechanism for a memory circuit. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a...
6594818 Memory architecture permitting selection of storage density after fabrication of active circuitry  
A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming...
6590812 Memory cells incorporating a buffer circuit and memory comprising such a memory cell  
A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a...
6590802 Semiconductor storage apparatus  
A semiconductor storage apparatus having an SRAM memory cell of a low power consumption type which can reduce a wiring length of a bit line. NMOS transistors (N 1 ), (N 3 ) and (N 4 ) are formed in...
6587369 Two-stage memory cell  
A memory cell is provided to store a speculative data value until either a later speculative data value is generated or until the stored speculative data is determined to be the desired data, e.g....
6580635 Bitline splitter  
During read operations of a column of RAM cells, a bitline is electrically broken into two sections. This reduces the capacitance that needs to be discharged by the RAM cell itself. A buffer is...
6577021 Static-type semiconductor memory device  
An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the...
6573773 Conflict free radiation tolerant storage cell  
A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the...
6570515 Decoder for reducing test time for detecting defective switches in a digital-to-analog converter  
A decoder for reducing a test time for detecting defective switches in a digital-to-analog converter includes a switch controlling portion for receiving a plurality of digital input signals having...
6563730 Low power static RAM architecture  
A static RAM bit cell and a system and method for operating an array of such static RAM bit cells. The static RAM bit cell herein includes a cell of four transistors configured to store data. It...
6563749 Dynamic memory circuit including spare cells  
A dynamic memory circuit including memory cells arranged in an array of rows and columns, each row capable of being activated by a word line and each column being formed of cells connected to a...
6560139 Low leakage current SRAM array  
An SRAM array is disclosed. The SRAM array includes a plurality of SRAM cells. In one embodiment, the SRAM cells are 6-T SRAM cells that further includes a voltage bias device. The voltage bias...
6560140 Single ended two-stage memory cell  
The present invention provides a memory array having an array structure that has at least one memory cell, including a word write bit line and a single transfer line. The memory array is also...
6556472 Static RAM with optimized timing of driving control signal for sense amplifier  
The present invention is a static RAM comprising a memory cell array having memory cells located at intersections of word lines and bit lines, and a sense amplifier for amplifying a voltage of the...
6556501 Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations  
A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the...
6556471 VDD modulated SRAM for highly scaled, high performance cache  
The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a...
6556487 Non-volatile static memory cell  
A non-volatile SRAM cell including (i) a nonvolatile memory element, (ii) a volatile memory element coupled to the nonvolatile memory element and (iii) a gate circuit coupled to the nonvolatile...
6552925 Method of reading a four-transistor memory cell array  
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an...
6552923 SRAM with write-back on read  
A data storage cell that is stable on standby but upsets on read. Standby stability is achieved without read and restore. In one embodiment, the leakage current is balanced by manipulating the...
6552924 Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns  
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an...
6549450 Method and system for improving the performance on SOI memory arrays in an SRAM architecture system  
The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode....
6549453 Method and apparatus for writing operation in SRAM cells employing PFETS pass gates  
A method for preparing a computer memory cell for a data write operation thereto is disclosed. The memory cell has a cell supply voltage source which is connected at one end to pull-up devices...
6549451 Memory cell having reduced leakage current  
A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor...
6549452 Variable width wordline pulses in a memory device  
A method for accessing an SRAM cell includes: determining whether an access is a read access or write access, applying a read word line pulse having a first width to a word line if the access is a...
6545297 High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown  
Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during...
6545905 Multi-port memory cell with refresh port  
A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to a second terminal of the storage...
6542401 SRAM device  
An SRAM device of the present invention is an SRAM device, including: a plurality of bit line pairs that are arranged substantially parallel to one another and connected to different memory cells,...
6542424 Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier  
A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a...
6542423 Read port design and method for register array  
A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data...
6535417 Semiconductor storage device  
An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and...
6528897 Semiconductor memory device  
A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially...
6529402 Low power static memory  
A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data...
6529400 Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells  
A source pulsed, dynamic threshold complementary metal oxide semiconductor static random access memory dynamically controls cell transistor threshold voltage to increase cell stability, decrease...
6529403 Integrated resistor having aligned body and contact and method for forming the same  
An integrated resistor includes a resistor body region and a resistor contact region that is aligned with the body region. Because the resistor includes an aligned body and contact, it often...
6525983 Device and method for reducing standby current in a memory device by disconnecting bit line load devices in unused columns of the memory device from a supply voltage  
Bit line load circuitry that eliminates wasted standby current flowing to an unused (i.e., repaired-out) column in a Static Random Access Memory (SRAM) device includes a fuse or an anti-fuse...
6519176 Dual threshold SRAM cell for single-ended sensing  
A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of...
6519177 Circuits and methods for initializing memory cells  
A memory initialization circuit includes one or more duplicated pairs of bit lines, which may be used to initialize the memory cells of a memory array to different logical values. When an...
6515895 Non-volatile magnetic register  
A non-volatile, bistable magnetic tunnel junction (MTJ) register cell includes first and second magnetic tunnel junctions connected for differential operation. The first MTJ is coupled between an...
Matches 701 - 750 out of 1780 < 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 >