Matches 651 - 700 out of 1780 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >
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6724676 Soft error improvement for latches  
Embodiments of the present invention generally provide a soft error-resistant latch circuit. The latch circuit generally includes first and second inverters, each formed by at least two...
6724647 Variable logical circuit, semiconductor integrated circuit, and method for manufacturing semiconductor integrated circuit  
A semiconductor integrated circuit (FPLA) having a desired logical function achieved by arranging on a semiconductor chip variable logical circuits each having n×n (e.g., four) memory cells...
6724650 Semiconductor device having a load less four transistor cell  
A unit memory cell comprises first and second field effect transistors of a first conduction type, third and fourth field effect transistors of a second conduction type, and first and second...
6724648 SRAM array with dynamic voltage for reducing active leakage power  
A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply...
6717874 Systems and methods for reducing the effect of noise while reading data in series from memory  
Systems and methods for reducing the effect of noise while reading data in series from memory, are provided. One system embodiment comprises a memory cell that stores a first data; a sensing device...
6717842 Static type semiconductor memory device with dummy memory cell  
The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of...
6717844 Semiconductor memory device with latch circuit and two magneto-resistance elements  
A memory cell in a MRAM includes four N channel MOS transistors responsive to a write permit signal attaining an H level to connect program lines of first and second tunneling magneto-resistance...
6717841 Semiconductor memory device having nonvolatile memory cell of high operating stability  
There is provided with A flip-flop circuit for setting one of first and second storage nodes at one of first and second potential levels and the other storage node at the other potential level in...
6714438 Semiconductor device with high speed latch operation  
A semiconductor device includes a first latch which receives an input signal, and holds the input signal during a half cycle period of a first clock signal, a delay element coupled to an output of...
6714478 Semiconductor memory device having divided word line structure  
A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the...
6711081 Refreshing of multi-port memory in integrated circuits  
A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh...
6711051 Static RAM architecture with bit line partitioning  
A SRAM system which provides for reduced power consumption. The SRAM system utilizes an array of bit cells. Columns of bit cells in the array are partitioned into sections. Each section of bit...
6711067 System and method for bit line sharing  
A system and method is provided for bit line sharing in a memory device. Adjacent memory cells are configured to share a bit line and are accessed with separate word lines as an odd and even plane....
6711069 Register having a ferromagnetic memory cells  
The invention generally related to registers or flip-flop circuits. More particularly, the present invention refers to the use of non-volatile ferromagnetic memory cell to store binary data in a...
6711070 Semiconductor memory device operating in synchronization with clock signal  
A comparator of a synchronous SRAM includes: n+1 EX-OR gates for detecting whether or not n+1 signals included in an address signal inputted in a cycle and n+1 signals included in an address signal...
6707708 Static random access memory with symmetric leakage-compensated bit line  
An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored...
6707702 Volatile memory with non-volatile ferroelectric capacitors  
Memory apparatus and methods are provided for storing data in a semiconductor device, comprising volatile and non-volatile portions, where the non-volatile portion comprises two ferroelectric...
6707721 Low power memory design with asymmetric bit line driver  
A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the...
6707692 Content addressable memory device capable of being used as binary CAM device or as ternary CAM device and structure method therefor  
A content addressable memory (CAM) device according to the present invention is configured with binary CAM cells capable of holding binary data “0” and “1”, and is capable of being used...
6707730 Semiconductor memory device with efficient and reliable redundancy processing  
A semiconductor memory device includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is...
6707709 Three transistor SRAM  
A static random access element is comprised of three transistors and two resistors. Two transistors have their gates and drains cross connected to the respective drains and gates of the opposite...
6707757 Apparatus for externally timing high voltage cycles of non-volatile memory system  
An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal...
6700823 Programmable common mode termination for input/output circuits  
Systems and methods provide common mode termination for input/output circuits. For example, common mode termination may be provided to a bank of input/output circuits by programmably coupling a bus...
6693815 Semiconductor associative memory  
An associative memory composed of plural chips or a single chip which is preferably used in the fields of bandwidth compression for video images in mobile communication terminals and artificial...
6687144 High reliability content-addressable memory using shadow content-addressable memory  
A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The...
6687145 Static random access memory cell and method  
A method for forming a scaled static random access memory (SRAM) cell ( 10 ) based on an initial SRAM cell for implementation in a technology scaled from an initial technology. The SRAM cells...
6683804 Read/write memory arrays and methods with predetermined and retrievable latent-state patterns  
Static read/write memory structures are provided that include predetermined latent-state patterns which can be retrieved with a latent-state retrieve process that differs somewhat from a...
6678202 Reduced standby power memory array and method  
A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a gate. The method includes providing...
6678188 Quad state memory design methods, circuits, and systems  
As the number of signaling wires increase in integrated circuits, power consumption, related to charging and discharging of wiring capacitance also increases and emerges as a serious obstacle to...
6674665 SONOS latch and application  
An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage...
6671197 Contest addressable memory (CAM) with tri-state inverters for data storage  
A memory device includes an array of memory cells. When in use, each cell can store a charge representing a binary digit of data. Data lines are connected to the memory cells. The data lines are...
6671202 Programmable circuit structures with reduced susceptibility to single event upsets  
Programmable circuit structures having reduced susceptibility to single event upsets. A circuit structure includes a programmable circuit controlled by a group of memory cells, of which at most one...
6671201 Method for writing data into a semiconductor memory device and semiconductor memory therefor  
A method of writing data into a semiconductor memory device including a memory cell to which a power supply potential and a ground potential are provided is disclosed. The method may include...
6667923 RAM data array configured to provide data-independent, write cycle coherent current drain  
An apparatus and method for forming a RAM data memory that generates predictable noise/interference components that are coherent with each write cycle and essentially independent of the data...
6665208 Semiconductor integrated circuit device including a cache having a comparator and a memory  
A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected...
6661732 Memory system having reduced powder data refresh  
The present invention discloses a memory whose power consumption for refresh is reduced to such a level as that of medium and low speed devices, such as SRAM, in its data retention mode. A...
6661687 Cam circuit with separate memory and logic operating voltages  
A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control at least some of the logic portions of...
6657243 Semiconductor device with SRAM section including a plurality of memory cells  
A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver...
6657887 Semiconductor memory device having improved noise margin, faster read rate and reduced power consumption  
A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells capable of improved noise margin, faster read rate and reduced power consumption is formed...
6657886 Split local and continuous bitline for fast domino read SRAM  
A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality...
6657885 Static semiconductor memory device  
A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided...
6654277 SRAM with improved noise sensitivity  
A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low β ratio for high performance....
6654276 Four-transistor static memory cell array  
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an...
6650580 Method for margin testing  
A method for testing semiconductor memory device using an active restore weak write test mode for resistive bitline contacts. During the write margin testing a test signal is used to block the...
6646938 Static memory having self-timing circuit  
A static memory including a memory cell array having word lines, bit line pairs, and memory cells, each having a pair of nodes holding opposite levels; includes a dummy circuit disposed along the...
6646909 Memory cell, nonvolatile memory device and control method therefor improving reliability under low power supply voltage  
For a memory cell comprising: a pair of memory nodes for holding a pair of complementary voltages; a pair of switching elements for controlling the connection between each memory node and a bit...
6643173 Semiconductor memory device operating in low power supply voltage and low power consumption  
A semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a...
6642743 System for rapid configuration of a programmable logic device  
A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a...
6643167 Semiconductor memory  
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I 1 ) consists of a NMOS transistor (N...
6643166 Low power SRAM redundancy repair scheme  
A particular SRAM cell power scheme is disclosed. It ensures that overall chip power is reduced, by eliminating power contributed by defective memory array cells. The VSS path to the 6T memory cell...
Matches 651 - 700 out of 1780 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >