|
Match
|
Document |
Document Title |
|
|
6891745 |
Design concept for SRAM read margin
A new method to improve the reading margin in a SRAM memory array is achieved. The method comprises providing an array of SRAM cells. Each SRAM cell has a power supply terminal. A first voltage is...
|
|
|
6888740 |
Two-transistor SRAM cells
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The...
|
|
|
6888202 |
Low-power high-performance storage circuitry
An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor...
|
|
|
6888741 |
Secure and static 4T SRAM cells in EDRAM technology
Disclosed herein is a 4T (four transistor) SRAM cells. Stability, fabrication and integration density advantages as well as a high degree of soft error immunity with small and potentially...
|
|
|
6888768 |
Semiconductor integrated device
A semiconductor integrated device which comprises a memory cell 20 holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in...
|
|
|
6885609 |
Semiconductor memory device supporting two data ports
A layout of a memory cell of a dual-port semiconductor memory device provides for one memory cell that includes a total of eight transistors, including two NMOS scan transistors. Among the...
|
|
|
6882562 |
Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
A method and apparatus operable to provide pseudo 2-port RAM functionality using 1-port memory cells. A pseudo 2-port RAM functionality is provided using an array of 1-port memory cells to perform...
|
|
|
6879531 |
Reduced read delay for single-ended sensing
An offset line to substantially cancel the capacitive coupling effects of a select line to a memory cell. When the select line transitions to cause a stored memory state in the memory cell to be...
|
|
|
6879511 |
Memory on a SOI substrate
A SRAM on an SOI substrate comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors, each cell being connected to two bit lines and to one of the...
|
|
|
6876572 |
Programmable logic devices with stabilized configuration cells for reduced soft error rates
Programmable logic devices are provided having configuration memory cells that exhibit decreased soft error rates. A stabilizing capacitor may be connected between each of the memory cell's input...
|
|
|
6876573 |
Semiconductor memory device
A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power...
|
|
|
6876571 |
Static random access memory having leakage reduction circuit
A static random access memory (SRAM) is provided that includes a logic circuit coupled to a column select signal line and a leakage reduction circuit coupled to the logic circuit and a bit line...
|
|
|
6873565 |
Dual-ported read SRAM cell with improved soft error immunity
In a preferred embodiment, the invention provides a circuit and method for improving the soft error rate in a dual-port read SRAM cell. A write-only transfer device is connected to a cross-coupled...
|
|
|
6870756 |
Semiconductor integrated circuit device
A semiconductor integrated circuit device provided with a SRAM realizing low power consumption and high speed is to be provided. Out of memory circuits which cause a timing generator circuit which...
|
|
|
6868000 |
Coupled body contacts for SOI differential circuits
A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs)...
|
|
|
6865129 |
Differential amplifier circuit with high amplification factor and semiconductor memory device using the differential amplifier circuit
A differential amplifier circuit includes a pair of first and second P-type transistors and a pair of first and second enhancement-mode N-type transistors. The first and second P-type transistors...
|
|
|
6865102 |
Static semiconductor storage device
A static semiconductor storage device is described. This device includes a plurality of word lines, a plurality of first and second bit lines and memory cells. The word lines extend in a row...
|
|
|
6865119 |
Negatively charged wordline for reduced subthreshold current
An invention is provided for reducing subthreshold current in memory core cells. A memory array having a plurality of memory core cells is provided. Each memory core cell in the memory array is...
|
|
|
6862207 |
Static random access memory
A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the...
|
|
|
6862226 |
Method of driving a non-volatile flip-flop circuit using variable resistor elements
A method of driving a non-volatile flip-flop circuit comprising a first inverter (INV 1 ) coupled to a first memory node ( 9 ) and a second memory node ( 10 ), a second inverter (INV 2 ) coupled to...
|
|
|
6862208 |
Memory device with sense amplifier and self-timed latch
A memory device ( 201 ) includes a plurality of memory cells ( 203 ), bit lines, word lines, a sense amplifier ( 314 ), and a self-timed latch ( 215 ). The sense amplifier ( 314 ), responsive to a...
|
|
|
6859386 |
Semiconductor memory device with memory cell having low cell ratio
In a memory cell, the cell ratio between an N-channel MOS transistor as a driver transistor and an N-channel MOS transistor as an access transistor is 1. To the first and second storage nodes,...
|
|
|
6859385 |
Low power SRAM
An SRAM has a bit cell for storing a data bit in voltage mode at a data node, and a single bit line for respectively writing to and reading from said data node a data bit in reference current...
|
|
|
6856555 |
Leak immune semiconductor memory
A semiconductor memory has word lines, bit lines, memory cells configured to store signals by transition states of transistors and configured to provide the bit lines with the signals addressed by...
|
|
|
6856031 |
SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD
A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal...
|
|
|
6853578 |
Pulse driven single bit line SRAM cell
A single bit line, pulse-operated memory cell. The memory cell includes a first and second inverter, write access and feedback-control transistors, and read access transistor and read buffer...
|
|
|
6853579 |
Non-refresh four-transistor memory cell
An exemplary four-transistor random access memory cell includes a first transistor of a first conductivity type having a gate coupled to a word line and a source coupled to a bit line, a second...
|
|
|
6847543 |
Non-volatile memory circuit, a method for driving the same, and a semiconductor device using the memory circuit
A non-volatile memory circuit comprising first and second transistors ( 101, 102 ) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains...
|
|
|
6847542 |
SRAM cell and integrated memory circuit using the same
An SRAM cell comprising a first inverter comprising a first load element and a first driver NMOSFET, a second inverter comprising a second load element and a second driver NMOSFET and having input...
|
|
|
6839268 |
Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system
A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection...
|
|
|
6839807 |
Multi-way set associative cache memory
A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select...
|
|
|
6836428 |
Semiconductor memory device including Shadow RAM
There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a...
|
|
|
6831853 |
Apparatus for cleaning a substrate
A memory device includes a number of memory cells 112 arranged in rows and columns. Each memory cell 112 is coupled to a wordline 120 and at least one bitline 126 and/or 128. Each bitline...
|
|
|
6829158 |
Magnetoresistive level generator and method
A magnetoresistive multi-level generator including a first series circuit with a first magnetoresistive element having a resistance equal to Rmax connected in series with n first magnetoresistive...
|
|
|
6829156 |
SRAM power-up system and method
A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells...
|
|
|
6826073 |
Combination of SRAM and MROM cells
A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different...
|
|
|
6826074 |
Semiconductor memory device
In a semiconductor memory device, a precharge potential for non-selected bit lines among a plurality of bit lines, supplied by a HPR voltage source, is set at a value (for example, ½ Vcc=0.4 V)...
|
|
|
6826730 |
System and method for controlling current in an integrated circuit
A circuit 10 is provided that comprises a source resistance transistor 12 connected to a common node 14 . A word line driver circuit 18 receives current if it is the word line driver...
|
|
|
6822894 |
Single event upset in SRAM cells in FPGAs with leaky gate transistors
A memory device having single event upset (SEU) resistant circuitry includes a first inverter having an input and an output, a second inverter having an input and an output, a first transistor...
|
|
|
6816401 |
Static random access memory (SRAM) without precharge circuitry
An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated...
|
|
|
6813180 |
FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A SRAM ARRAY, A COMPUTER SYSTEM, A PROCESS FOR FORMING A SRAM CELL, A PROCESS FOR TURNING A SRAM CELL OFF, A PROCESS FOR WRITING A SRAM CELL AND A PROCESS FOR READING DATA FROM A SRAM CELL
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The...
|
|
|
6813179 |
Cache memory
An integrated cache memory circuit is provided comprising a tag RAM, a comparator and a data RAM. Each of the tag RAM and the date RAM have an array of memory cells and plural sense amplifiers....
|
|
|
6809945 |
Content addressable memory match line sensing techniques
A content addressable memory ( 10 ) comprising a group of content addressable cells ( 20 ) and a group of corresponding match switches ( 30 ) coupled by a first match line ( 36 ) that is switched...
|
|
|
6804132 |
Circuit for multiple match hit CAM readout
An apparatus for reading out multiple match hits from a content addressable memory (CAM), comprising a priority encoder for receiving a plurality of matchlines from a CAM and for encoding addresses...
|
|
|
6804143 |
Write-assisted SRAM bit cell
An SRAM bit cell with cross-coupled inverters has separate write and read buses. Writing is performed through an NMOS pass transistor. Reading is performed through a PMOS transistor. Because the...
|
|
|
6801449 |
Semiconductor memory device
A semiconductor memory device according to an aspect of the present invention includes memory cells each having a data storage section which stores data and a transfer gate section which has a...
|
|
|
6801463 |
Method and apparatus for leakage compensation with full Vcc pre-charge
A leakage compensation approach enabling full V CC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially...
|
|
|
6798700 |
Methods of reading and/or writing data to memory devices including multiple write circuits and/or virtual ground lines and related devices
Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit...
|
|
|
6798688 |
Storage array such as a SRAM with reduced power requirements
A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD)...
|
|
|
6798704 |
High Speed sense amplifier data-hold circuit for single-ended SRAM
A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays having plural memory cells, a sense...
|