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6972987 Techniques for reducing power consumption in memory cells  
Techniques are provided for reducing power consumption in memory cells. A static (SRAM) memory cell includes two cross coupled inverters. One or more transistors are coupled between the inverters...
6970374 Low leakage current static random access memory  
A static random access memory (SRAM) has a plurality of SRAM cells, a first switch unit, a second switch unit, and a capacitor. During read/write operations of the SRAM cells, the first switch unit...
6967857 Dense content addressable memory cell  
A content addressable memory cell ( 10 ) comprises a word line 12 , a first bit line ( 14 ), and a second bit line ( 16 ). A pair of transistors ( 30–31 ) is arranged to store bits of data at...
6968486 Master-slave-type scanning flip-flop circuit for high-speed operation with reduced load capacity of clock controller  
A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used...
6967861 Method and apparatus for improving cycle time in a quad data rate SRAM device  
A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current...
6965524 Non-volatile static random access memory  
In accordance with the present invention, a memory cell includes a non-volatile device and a SRAM cell. The SRAM cell includes first and second MOS transistors. The non-volatile device is a load to...
6963222 Non-volatile product term (pterm) cell  
A non-volatile product term cell is provided having a first floating gate located over a first p-channel transistor and a first n-channel transistor, and a second floating gate located over a...
6963499 Static RAM with flash-clear function  
A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies,...
6963509 Page buffer having dual register, semiconductor memory device having the same, and program method thereof  
The present invention discloses a page buffer having a dual register, a semiconductor memory device having the same, and a program method thereof. A data transmission path is formed by installing...
6956784 Writable memory  
A memory is provided in which each memory cell can be in a first state or a second state, and those cells which should be in the first state always correctly power up into that state whereas cells...
6954377 Non-volatile differential dynamic random access memory  
In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM...
6952363 Semiconductor memory device with selectively connectable segmented bit line member and method of driving the same  
A semiconductor memory device, that reduces load capacitance of write-only bit lines, may include: a first bit cell array block, in which bit cells thereof are defined by intersections of first bit...
6950355 System and method to screen defect related reliability failures in CMOS SRAMS  
A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g.,...
6950366 Method and system for providing a low power memory array  
A method for providing a low power memory array is provided. The method includes partitioning a memory array into at least two memory sections. Each memory section comprises a plurality of memory...
6950359 Memory bit line leakage repair  
Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit...
6947310 Ferroelectric latch  
Ferroelectric latch type memory devices ( 102 ) are provided, comprising an input circuit ( 110 ) with first and second internal nodes (N 1 , N 2 ) coupled with first and second ferroelectric...
6947321 Organic thin-film switching memory device and memory device  
An organic switching memory device includes a plurality of first electrode lines; an organic memory layer formed on the plurality of first electrode lines, the organic memory layer having a...
6944050 Nonvolatile memory device  
The present invention relates to a nonvolatile memory device, and more specifically, to a programmable nonvolatile logic switch memory (register) device using a resistive memory device. The...
6944784 Flip-flop having multiple clock sources and method therefore  
Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals...
6944042 Multiple bit memory cells and methods for reading non-volatile data  
Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are...
6940746 Semiconductor memory device  
A semiconductor memory device includes first and second CMOS (complementary metal oxide semiconductor) inverter circuits each having a latch structure and a control transistor which is connected...
6940778 System and method for reducing leakage in memory cells using wordline control  
An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the...
6940739 Semiconductor memory device  
A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The...
6937492 Reducing signal swing in a match detection circuit  
The present invention provides a content addressable memory (CAM) match detection circuit that maintains traditionally achieved levels of accuracy while greatly reducing the amount of power...
6937503 1T1C SRAM  
Memory circuits and methods are described providing an interface with high density dynamic memory (DRAM), such 1T1C (1 transistor and 1 capacitor) memory cells, providing full compatibility with...
6934182 Method to improve cache capacity of SOI and bulk  
Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs),...
6934181 Reducing sub-threshold leakage in a memory array  
A method and memory array for reducing sub-threshold leakage in a memory array. A memory array may include a plurality of rows where each row may include one or more groups of cells. Within each...
6930953 Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory bandwidth  
A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates...
6930941 Semiconductor memory device having potential amplitude of global bit line pair restricted to partial swing  
A local sense amplifier drives a global bit line pair by potentials of data storage nodes when a global word line attains an H level. A global sense amplifier amplifies the potential difference of...
6920061 Loadless NMOS four transistor dynamic dual Vt SRAM cell  
Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data...
6917556 Static memory cell having independent data holding voltage  
A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the...
6917536 Memory access circuit and method for reading and writing data with the same clock signal  
A read operation and a write operation are synchronized via one port of a memory cell to avoid contention between such operations while doubling the bandwidth of such operations. Data is read from...
6917537 RSFQ Batcher-banyan switching network  
Superconductor technology and Batcher banyan switching technology are combined and implemented as a practical component in a single cryo-MCM substrate ( 10 ) containing a plurality of...
6914255 Phase change access device for memories  
A memory may have access devices formed using a chalcogenide material. The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being...
6914803 Low-power semiconductor memory device  
A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI...
6914797 Semiconductor memory  
First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to...
6914804 Memory cells enhanced for resistance to single event upset  
Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch,...
6909652 SRAM bit-line reduction  
A SRAM with reduced subthreshold leakage current, the SRAM including a pMOSFET with its gate at V SS and its source at V CC , and a diode-connected pMOSFET with its source at V CC , where the...
6909627 Apparatus turning on word line decoder by reference bit line equalization  
A memory comprising a memory array, a plurality of word lines, a plurality of bit lines, a word line decoder, an equalizer and an equalization control apparatus is provided to meet the requirement...
6909663 Multiport memory with twisted bitlines  
Memory cell arrays are defined by rows and columns of memory cells that are addressed by sets of bitlines associated with a first memory port and a second memory port. The bitlines associated with...
6909637 Full rail drive enhancement to differential SEU hardening circuit while loading data  
A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the...
6906937 Bit line control circuit for a content addressable memory  
A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for...
6906962 Method for defining the initial state of static random access memory  
A method for predetermining the initial state of the memory cells of a static random access memory such that when the memory is powered up the predetermined initial states are attained. The initial...
6903952 Content addressable memory cell techniques  
A content addressable memory cell ( 10 ) includes a circuit ( 20 ) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point ( 35 ) and a second bit of...
6903996 Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme  
The present invention relates to storage element. At least one read port is coupled to the storage element and a sensing device is coupled to the read port, where the read port is coupled to the...
6901017 Semiconductor memory having hierarchical bit line structure  
A first amplifier amplifies voltage of a first local bit line connected to static memory cells. Precharging circuits for precharging a first global bit line connected to an output of the first...
6901004 High voltage switch circuitry  
The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high...
6901016 Semiconductor memory device and electronic instrument using the same  
A semiconductor memory device has a first precharge transistor connecting a potential supply line to one end of a bit line when the bit line is precharged and a second precharge transistor...
6901003 Lower power and reduced device split local and continuous bitline for domino read SRAMs  
A method, an apparatus, and a computer program are provided to reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line....
6898111 SRAM device  
In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors...
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