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Match Document Document Title
7619271 Deep trench device with single sided connecting structure and fabrication method thereof  
A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An...
7616515 Integrated electronic device having a low voltage electric supply  
An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the...
7613025 Dram cell design with folded digitline architecture and angled active areas  
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an...
7609567 System and method for simulating an aspect of a memory circuit  
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such...
7609551 Semiconductor memory device  
This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region...
7609546 Multivalue memory storage with two gating transistors  
Digital memory devices and systems, as well as methods of operating digital memory devices, that include a multivalue memory cell with a first and a second gating transistor arranged in parallel,...
7602658 RFID device having nonvolatile ferroelectric memory device  
A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block...
7602634 Dynamic RAM storage techniques  
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a...
7599212 Method and apparatus for high-efficiency operation of a dynamic random access memory  
The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line....
7596038 Floating body control in SOI DRAM  
A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a...
7595532 Semiconductor memory devices and methods of forming the same  
A semiconductor memory device includes a semiconductor substrate including an insulating layer, a charge storage region of a first conductivity type on the insulating layer, and an insulating film...
7590017 DRAM bitline precharge scheme  
Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing...
7589995 One-transistor memory cell with bias gate  
One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a...
7586779 Controller apparatus for utilizing downgrade memory and method for operating the same  
A controller apparatus for utilizing downgrade memory and method for operating the same are proposed. The controller apparatus uses address assignment to access the downgrade memory, which is...
7580314 Memory device having open bit line structure and method of sensing data therefrom  
A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the...
7580304 Multiple bus charge sharing  
A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first...
7577041 Semiconductor memory device and writing method thereof  
A semiconductor memory device includes a power supply circuit which generates a write current, a write line to which a logic state is transferred, a first pass transistor connected between the...
7573768 Low voltage semiconductor memory device  
A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and...
7573749 Counteracting overtunneling in nonvolatile memory cells  
Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge,...
7570533 Completely transportable erasable memory apparatus and method  
The present invention relates to methods and apparatuses for providing data storage which can be completely erased to prevent access to previously stored data.
7567452 Multi-level dynamic memory device having open bit line structure and method of driving the same  
A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an...
7567451 Ferroelectric memory device and electronic equipment  
A ferroelectric memory device, having: a first charge-transfer MISFET, connected between a first bit line and a first node; a second charge-transfer MISFET, connected between a second bit line and...
7566613 Method of forming a dual gated FinFET gain cell  
A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell...
7564709 Method and system for utilizing DRAM components in a system-on-chip  
A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the...
7564086 Self-aligned, silicided, trench-based DRAM/eDRAM processes with improved retention  
A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and...
7561462 Circuit and method for a high speed dynamic RAM  
An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the...
7558134 Semiconductor memory device and its operation method  
A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit...
7558102 Device and method having a memory array storing each bit in multiple memory cells  
A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory...
7554833 Semiconductor memory and method of writing data into the semiconductor memory  
A non-volatile semiconductor memory including a silicon substrate having first and second diffusion layers at its surface and a control gate located above a channel region defined by the first and...
7551495 Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof  
The example semiconductor memory device may include a memory cell, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a...
7551474 DRAM including a reduced storage capacitor  
A reduced storage capacitor is used for shrinking a memory cell in DRAM, and local bit line is divided into short line for reducing parasitic capacitance. For reading, a first reduced swing...
7548454 Memory array with readout isolation  
Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array....
7548447 Semiconductor memory device and methods thereof  
A semiconductor memory device and methods thereof. The example semiconductor memory device may include a semiconductor substrate, a first source line and a second source line oriented in a first...
7542328 Method of detecting bit line bridge by selectively floating even-or odd-numbered bit lines of memory device  
Provided is a bit line bridge detection method for selectively floating even-numbered or odd-numbered bit lines. The bit line bridge detection method simultaneously activates even-numbered sense...
7542327 Measuring method for a semiconductor memory, and semiconductor memory  
The invention relates to a semiconductor memory, and to a measuring method for a semiconductor memory. In one case, the method includes connecting a memory cell to a ring oscillator and measuring...
7542325 Ferroelectric memory  
A ferroelectric memory comprises a memory cell block of plural serially connected memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel therewith. And...
7541614 Integrated circuit, semiconductor device comprising the same, electronic device having the same, and driving method of the same  
An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a...
7539048 Method and apparatus processing variable resistance memory cell write operation  
A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking device and a charge storing element. As...
7539044 Memory device with capacitor and diode  
One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a charge or voltage. The capacitor...
7539042 Semiconductor device and fabrication method thereof  
The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be...
7539041 Floating body semiconductor memory device and method of operating the same  
A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is...
7535749 Dynamic memory word line driver scheme  
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word...
7532500 Method and apparatus for storing data and method for reading data  
An apparatus and method for storing data, and a method for reading data. The apparatus for storing data of the present invention comprises at least one bridge for storing binary data. Each bridge...
7532496 System and method for providing a low voltage low power EPROM based on gate oxide breakdown  
A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor and a PMOS program transistor...
7529141 Asynchronous, high-bandwidth memory component using calibrated timing elements  
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an...
7529116 Memory device having a threshold voltage switching device and a method for storing information in the memory device  
Disclosed herein is a memory device having an increased level of integration with a simplified method of manufacture. The memory device includes: a plurality of word lines and a plurality of bit...
7529115 Ferroelectric memory device, electronic apparatus, and ferroelectric memory device driving method  
A ferroelectric memory device including: a plurality of bit lines; a plurality of memory cells, which are connected to the bit lines, and which store prescribed data; and a sense amplifier, which...
7525141 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines  
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a...
7522456 Non-volatile memory embedded in a conventional logic process and methods for operating same  
A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate...
7521744 Resin-encapsulated semiconductor apparatus and process for its fabrication  
The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member...
Matches 1 - 50 out of 1902 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >