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6853600 Ferro-electric random access memory using paraelectric and ferroelectric capacitor for generating a reference potential  
A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC 1 and a ferro-electric capacitor DCC 2 . One end of the paraelectric capacitor DCC 1 and one end...
6853575 Cell array of FeRAM  
A cell array of a NAND type ferro-dielectric memory is disclosed. The cell array of ferro-dielectric memory system, including: a plurality of unit cell strings coupled to one bit line; and a...
6853576 Semiconductor device, method for fabricating the same, and method for driving the same  
A semiconductor memory device has a plurality of memory cells each having a first ferroelectric capacitor for storing data as a polarization value. First voltage applying means applies a first read...
6847534 High density dynamic ternary-CAM memory architecture  
A ternary CAM memory device is disclosed which comprises a pair of complementary compare lines, a pair of complementary bit lines, and a unique four transistor two capacitor circuit.
6847540 Semiconductor memory device and control method thereof  
A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell...
6847573 Synchronous SRAM-compatible memory device including DRAM array with internal refresh  
The synchronous SRAM-compatible memory includes a DRAM array, a data input/output unit, an address input unit, a burst address generating unit, a state control unit, a refresh timer, and a refresh...
6845033 Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology  
A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM...
6845052 Dual reference cell sensing scheme for non-volatile memory  
The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense...
6845035 Semiconductor memory device  
A semiconductor memory device uses memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability. A semiconductor memory...
6845034 Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons  
Electronic systems Si/Ge substrates. The electronic systems can include data storage devices and/or logic devices having active regions extending into a crystalline Si/Ge material. An entirety of...
6841818 Non-volatile memory device utilizing dueterated materials  
In a non-volatile memory device that includes an electrically polarizable dielectric memory material with ferroelectric or electret properties and capable of exhibiting hysteresis and remanence,...
6839267 Structure and method of multiplexing bitline signals within a memory array  
An integrated circuit memory is provided in which a multiplexer is operable to select one of a plurality of bitlines to couple to a master bitline using select transistors of an array of...
6836419 Split word line ternary CAM architecture  
A content addressable memory (CAM) cell which has a split word line scheme and having binary and ternary storage capability. The cell has a pair of storage devices, a comparing circuit, a pair of...
6836427 System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems  
The disclosed system and method introduce voltage disturbances into a reference sub-array to offset voltage disturbances occurring in an active sub-array. The disclosed system and method connect...
6836425 CODING CELL OF NONVOLATILE FERROELECTRIC MEMORY DEVICE AND OPERATING METHOD THEREOF, AND COLUMN REPAIR CIRCUIT OF NONVOLATILE FERROELECTRIC MEMORY DEVICE HAVING THE CODING CELL AND METHOD FOR REPAIRING COLUMN  
A fail repair circuit of a nonvolatile ferroelectric memory device and a method for repairing the same are disclosed, in which a redundancy time can be reduced and a redundancy algorithm can be...
6831852 Semiconductor memory device having a latch circuit and storage capacitor  
A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically...
6826094 Magnetic memory cell sensing with first and second currents  
A magnetic memory includes a sense amplifier coupled to a memory cell. The sense amplifier includes a capacitor operative between a first voltage established by a first sense current flowing in a...
6822920 SRAM-compatible memory device employing DRAM cells  
Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a...
6819581 Ferroelectric nonvolatile semiconductor memory  
A ferroelectric-type nonvolatile semiconductor memory comprises a bit line BL 1 , a transistor for selection TR 1 , (C) a memory unit MU 1 composed of memory cells that are M in number (M≧2),...
6816398 Memory device  
A memory device capable of improving the degree of integration and effectively preventing false data reading is obtained. This memory device comprises a pair of bit lines extending in a prescribed...
6816400 Circuit and method for testing a ferroelectric memory device  
A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines,...
6816399 Semiconductor memory device including ferroelectric memory formed using ferroelectric capacitor  
A semiconductor memory device includes a memory cell block, gate lines and branch lines. The memory cell block includes memory cells connected in series. Each of memory cells has a cell transistor...
6813205 Pre-charge and sense-out circuit for differential type ROM  
A pre-charge and sense out circuit for differential type ROM. The ROM is capable of connecting to either a first bit line or a second bit line. The pre-charge and sense out circuit contains a...
6809978 Implementation of a temperature sensor to control internal chip voltages  
A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a...
6809953 Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof  
A potential generating circuit comprises a capacitor ( 4 ); a ferroelectric capacitor ( 6 ) connected in series to the capacitor ( 4 ); an output terminal ( 11 ); a capacitor ( 10 ) for grounding...
6809951 Ferroelectric semiconductor memory  
A ferroelectric semiconductor memory includes a cell array in which a plurality of ferroelectric memory cells are arranged in a matrix format, and a circuit section. Each memory cell includes a...
6809954 Circuit and method for reducing access transistor gate oxide stress  
A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first 106 and a second 110 control terminal...
6807604 Method of refreshing a dynamic memory  
A method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor, includes a step of planning 10 in the course of which an order and a timing...
6807113 Clamping circuit for the VPOP voltage used to program antifuses  
A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated...
6804140 Capacitance sensing method of reading a ferroelectric RAM  
A capacitance sensing method of reading a FeRAM (Ferroelectric Random Access Memory). First, enable the word line for turning on the first and the second switches. Then, enable the latch sense...
6801462 Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices  
A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are...
6801467 DRAM cell refreshment method and circuit  
A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing...
6801445 Multiple level RAM device  
A multiple level logic memory device is achieved. The device comprises, first, a plurality of memory cells capable of storing an analog voltage. Second, there is included a means of converting an...
6798687 System and method for effectively implementing a high speed DRAM device  
A system and method for effectively implementing a high-speed DRAM device may include memory cells that each have a bitline for transferring storage data, a wordline for enabling an...
6798686 Semiconductor device  
In a semiconductor memory device comprising a cell array of memory cells each including a cell transistor and a capacitor, word lines and bit line pairs, the control circuit controls the memory...
6798681 DRAM  
A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three...
6795331 Ferroelectric memory wherein bit line capacitance can be maximized  
In a ferroelectric memory, there are provided a plurality of word lines, a plurality of bit lines crossing there-with, a plurality of memory cells having ferroelectric capacitors arranged at the...
6795329 Memory integrated circuit  
An improved memory IC whose memory cells are configured in a chain architecture is disclosed. The first diffusion regions of the cell transistors of the chain are coupled to first capacitor...
6791891 Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage  
A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by...
6791861 Ferroelectric memory device and a method for driving the same  
A ferroelectric memory device includes a plurality of wordlines and a plurality of plate lines, the wordlines and the plate lines being alternately formed at regular intervals in one direction; a...
6788574 Electrically-alterable non-volatile memory cell  
A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a...
6788590 Bitline reference voltage circuit  
A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for...
6788563 Sensing device for a passive matrix memory and a read method for use therewith  
A sensing device for reading data stored in a passive matrix memory including memory cells in the form of ferroelectric capacitors, includes an integrator circuit for sensing the current response...
6788564 Ferroelectric storage apparatus, driving method therefor, and driving circuit therefor  
The invention provides a ferroelectric storage apparatus which can reduce or prevent disturbance, a driving method therefor, and a driving circuit therefor. In the ferroelectric storage apparatus,...
6785157 Semiconductor memory device having a memory cell structure of reduced occupying area  
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a...
6785179 Charge sharing between bit lines within a memory circuit to increase recharge speed  
A memory circuit 2 includes a plurality of memory cells 4, 6 which are subject to memory access operations. These memory access operations serve to selectively discharge one or more of the bit...
6785153 Tertiary CAM cell  
A tertiary CAM cell with three bits of storage, the three bits of storage are arranged to support three stable states which can be read from the CAM cell without requiring a charge restoration...
6785167 ROM embedded DRAM with programming  
Programming efficiency of a read only memory (ROM) embedded dynamic random access memory (DRAM) is improved by programming only one polarity of bits in non-volatile cells of the ROM embedded DRAM,...
6781866 Semiconductor memory and writing method and reading method for the same  
A semiconductor memory includes bit lines, memory cells and a sense amplifier both of which are connected to the bit lines. Each of the memory cells includes a transistor and a capacitor. The...
6781865 Nonvolatile selector, and integrated circuit device  
A multiplexer includes first through fourth switching sections 10 A through 10 D in a pre-stage gate and each of the switching sections 10 includes a serial capacitor 3 and a FET 4 . The...
Matches 401 - 450 out of 1910 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >