Matches 351 - 400 out of 1911 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6940740 Multilevel semiconductor memory device and method for driving the same as a neuron element in a neural network computer  
A semiconductor device includes: a control-voltage supply unit 110 ; an MOS transistor including a gate electrode 109 and drain and source regions 103 a and 103 b ; a dielectric capacitor ...
6937503 1T1C SRAM  
Memory circuits and methods are described providing an interface with high density dynamic memory (DRAM), such 1T1C (1 transistor and 1 capacitor) memory cells, providing full compatibility with...
6936876 Semiconductor device having ferroelectric thin film and fabricating method therefor  
A ferroelectric capacitor in a semiconductor device is constructed of a Pt lower electrode, a ferroelectric thin film and a Pt upper electrode that are successively laminated onto a silicon...
6934212 Semiconductor apparatus  
A simply structured, and highly reliable semiconductor apparatus having a large storage capacity. The apparatus has a plurality of memory cells on one semiconductor substrate, each including a...
6934180 Random access memory cell having reduced current leakage and having a pass transistor control gate formed in a trench  
A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( 300 ) includes a storage capacitor ( 304 ) and a pass transistor ( 302 ). The pass transistor ( 302 )...
6934211 DRAM with refresh control function  
A dynamic random access memory (DRAM) has a refresh-control function under control by an internal refresh-control signal. The DRAM includes: a cell array having a plurality of DRAM cells divided...
6924995 CAM circuit with radiation resistance  
A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on...
6922351 Ferroelectric memory device and method of manufacturing the same  
A ferroelectric memory device includes first electrodes, second electrodes arranged in a direction which intersects the first electrodes, and ferroelectric films disposed in at least intersecting...
6920059 Reducing effects of noise coupling in integrated circuits with memory arrays  
A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are...
6920077 Graphics controller integrated circuit without memory interface  
A CMOS integrated circuit which has a graphics controller system that has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for...
6917551 Memory devices, sense amplifiers, and methods of operation thereof using voltage-dependent capacitor pre-amplification  
A memory device includes a memory cell configured to be coupled to complementary first and second bit lines and a differential amplifier having first and second input terminals and operative to...
6916711 EEPROM memory cell and method of forming the same  
An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a...
6917052 Modified contact for programmable devices  
In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a...
6914840 Semiconductor memory circuit  
Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level,...
6914836 Sense amplifier circuits using a single bit line input  
An integrated circuit memory device can include a memory cell circuit configured to store data and a sense amplifier circuit configured to sense and amplify the stored data provided as a first...
6912150 Reference current generator, and method of programming, adjusting and/or operating same  
There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment...
6908808 Method of forming and storing data in a multiple state memory cell  
A method for forming a multiple state memory cell is provided. The method including forming a first electrode layer from a first conductive material, forming a second electrode layer from a second...
6909626 Method and related circuit for accessing locations of a ferroelectric memory  
A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by...
6906945 Bitline precharge timing scheme to improve signal margin  
A memory circuit and method to improve signal margin is disclosed. The circuit includes a memory array arranged in rows 702, 704, 706 and columns 750, 752 of memory cells. Each row of memory...
6903961 Semiconductor memory device having twin-cell units  
Each of twin-cell units each formed of two DRAM cells has a cell plate electrically isolated from the cell plates in the other twin-cell units. Thereby, voltages on two storage nodes storing...
6903959 Sensing of memory integrated circuits  
A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on...
6903957 Half density ROM embedded DRAM  
A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data...
6901018 Method of generating initializing signal in semiconductor memory device  
A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of...
6901002 Ferroelectric memory  
A ferroelectric memory capable of suppressing false data reading or the like by increasing a read margin is obtained. This ferroelectric memory comprises a circuit applying a read voltage V R to a...
6898110 Semiconductor integrated circuit device  
In a device including regular circuits and redundant circuits, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer...
6898105 Ferroelectric non-volatile memory device having integral capacitor and gate electrode, and driving method of a ferroelectric non-volatile memory device  
A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the...
6898140 Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors  
A memory system is provided that includes an array of memory cells that require periodic refresh, and a temperature-adaptive refresh controller. Data retention time of the memory cells decreases...
6898138 Method of reducing variable retention characteristics in DRAM cells  
The illustrated embodiments relate to reducing variable retention time in dynamic random access memory (DRAM) integrated circuit devices. Memory cells that comprise the DRAM device are placed in a...
6898109 Semiconductor memory device in which bit lines connected to dynamic memory cells extend left and right of sense amplifier column  
In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a...
6898137 Semiconductor memory device with high-speed sense amplifier  
In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a...
6894917 DRAM refresh scheme with flexible frequency for active and standby mode  
The present invention provides a method and an apparatus for DRAM refresh with different frequencies of refresh for active and standby mode. In addition, this invention utilizes different refresh...
6894918 Shared volatile and non-volatile memory  
The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to...
6891743 Semiconductor memory device having a capacitive plate to reduce soft errors  
A CMOS-SRAM has a plurality of full CMOS type memory cells ( 1 ) and a capacity plate ( 2 ). The memory cells ( 1 ) are two-dimensionally arranged in the row direction and in the column direction....
6888741 Secure and static 4T SRAM cells in EDRAM technology  
Disclosed herein is a 4T (four transistor) SRAM cells. Stability, fabrication and integration density advantages as well as a high degree of soft error immunity with small and potentially...
6885608 Multi-port memory circuit  
A memory cell includes first and second NMOS transistors and a capacitor that forms a storage node. During write operation, the first transistor is turned ON by a write address select circuit and a...
6885574 Low fatigue sensing method and circuit for ferroelectric non-volatile storage units  
A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for...
6885597 Sensing test circuit  
A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a...
6882561 Semiconductor memory device comprising memory having active restoration function  
A semiconductor memory device includes a sense line, a data line, a memory connected between the sense line and the data line having an active restoration function, and a sense amplifier connected...
6882587 Method of preparing to test a capacitor  
As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the...
6882560 Reading ferroelectric memory cells  
A first fraction of a programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source...
6876569 Semiconductor integrated circuit device with improved storage MOSFET arrangement  
A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a...
6870753 Ferroelectric memory  
A ferroelectric memory capable of multi-value memory retention is provided which hardly modifies a related art circuit. The period for which a write pulse is applied changes depending upon a value...
6867997 Series feram cell array  
Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a...
6867998 Cell array block of FeRAM, and FeRAM using cell array  
The present invention discloses a cell array block of a ferroelectric random access memory (FeRAM) and an FeRAM using the same. In the multi-bit line structure cell array block of the FeRAM having...
6865131 Memory devices with reduced power consumption refresh cycles  
Systems, devices, structures, and methods are described that reduce energy consumption during a refresh cycle in a memory device. An isolation signal is held in a non-energized state until the it...
6862205 Semiconductor memory device  
The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to...
6862204 Semiconductor integrated circuit having connecting wires for interconnecting bit lines  
A plurality of memory cell arrays includes bit lines and memory cells each constituted by a variable capacitor, and operates at mutually different timings. The bit lines of each memory cell array...
6859384 Semiconductor memory device having two-transistor, one-capacitor type memory cells of high data holding characteristic  
An active region which forms two transistors included in a memory cell is arranged to have a strip shape along a predetermined axis crossing first and second bit lines at less than 90 degrees,...
6859403 Semiconductor memory device capable of overcoming refresh disturb  
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first...
6856562 Test structure for measuring a junction resistance in a DRAM memory cell array  
A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active...
Matches 351 - 400 out of 1911 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >