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7443714 |
DRAM including segment read circuit
A time-domain sensing scheme is introduced for reading a DRAM cell and bit lines are multi-divided for reducing parasitic loading. Thereby lightly loaded bit line is quickly charged by a selected...
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7443713 |
Integrated semiconductor memory and method for operating a semiconductor memory
An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes...
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7440309 |
Memory having parity error correction
A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first...
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7440311 |
Single-poly non-volatile memory cell
A non-volatile memory cell includes a floating gate transistor having a floating gate coupled to a metal layer capacitor defined in one or more metal layers. Within each metal layer, the metal...
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7440307 |
Memory
This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a...
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7440310 |
Memory cell with trenched gated thyristor
One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward...
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7440334 |
Multi-transistor memory cells
A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in...
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7440347 |
Circuit and method to find wordline-bitline shorts in a DRAM
Method and apparatus for testing for a short between a wordline being tested and a bitline in a memory device. The method includes applying a first voltage to the bitline using a first voltage...
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7436691 |
Semiconductor storage device, operation method of the same and test method of the same
A semiconductor storage device includes a bit line; a word line; a plate line; a ferroelectric capacitor having a ferroelectric substance between electrodes, one of the electrodes being connected...
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7433223 |
Memory devices including floating body transistor capacitorless memory cells and related methods
In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body...
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7430151 |
Memory with clocked sense amplifier
In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory...
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7423923 |
Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to...
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7411810 |
One-time programmable memory
In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is...
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7411849 |
Apparatus and method for transferring an analog signal between isolated systems
An apparatus and method for transferring a signal from a first bus circuit to a second bus circuit. The apparatus and method includes a first constant current circuit connected to the first bus...
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7408828 |
System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices
A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage...
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7397692 |
High performance single event upset hardened SRAM cell
An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second...
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7397687 |
Ferroelectric memory device having ferroelectric capacitor
A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one...
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7394677 |
Ferroelectric random access memory device, display drive IC and electronic equipment
A ferroelectric memory device being short in the bit line direction. The ferroelectric memory device is structured including a first word line extending in the first direction; a plurality of...
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7391640 |
2-transistor floating-body dram
A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating...
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7388796 |
Method for testing memory under worse-than-normal conditions
A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than...
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7382641 |
FeRAM for high speed sensing
A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense...
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7376000 |
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets
Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable...
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7375999 |
Low equalized sense-amp for twin cell DRAMs
Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a first bitline and a second bitline....
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7376018 |
Non-volatile memory device with single transistor memory cell
A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell includes a floating gate transistor...
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7376030 |
Memory sensing circuit and method for low voltage operation
A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line...
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7372756 |
Non-skipping auto-refresh in a DRAM
In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This causes a remapping circuit to remap a...
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7372719 |
DRAM semiconductor memory device with increased reading accuracy
A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and second bit lines are connected to a...
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7369425 |
Method and system for DRAM sensing
This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass...
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7366052 |
Memory device, memory system and method of inputting/outputting data into/from the same
A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first...
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7355880 |
Soft error resistant memory cell and method of manufacture
A semiconductor device memory cell ( 100 ) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell ( 100 ) can include a first inverter ( 102 ) and second inverter (...
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7352617 |
Nano tube cell and memory device using the same
A nano tube cell and a memory device using the same features a cross point cell using a capacitor and a PNPN nano tube switch to reduce the whole memory size. In the memory device, the unit nano...
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7352604 |
Memory and driving method of the same
According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof...
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7349237 |
Plateline driver with RAMP rate control
A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows ( 702, 704 , and 706 ) and columns ( 750, 752 ). A first...
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7349275 |
Semiconductor memory
A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP 1 , capacitor C 1 , MOS transistor TP 2 , and control...
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7349282 |
Power voltage supplier of semiconductor memory device
The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the...
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7349232 |
6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an...
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7345906 |
Read method and sensing device
In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means...
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7345945 |
Line driver circuit for a semiconductor memory device
A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a...
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7342842 |
Data storage device and refreshing method for use with such device
A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents...
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7339849 |
Internal voltage supply circuit of a semiconductor memory device with a refresh mode
An internal voltage supply circuit may Include a first internal voltage generator for receiving an external voltage and generating a first internal voltage, a second internal voltage generator for...
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7336521 |
Memory pumping circuit
A memory pumping circuit is proposed. The feature of the present invention is the charging capacitor of the pumping circuit is a DRAM cell for enhancing the capacitance.
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7336523 |
Memory device using nanotube cells
A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory...
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7336522 |
Apparatus and method to reduce undesirable effects caused by a fault in a memory device
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline...
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RE40075 |
Method of multi-level storage in DRAM and apparatus thereof
A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a...
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7333370 |
Method to prevent bit line capacitive coupling
Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate,...
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7327596 |
Electrostatic capacitance detection device and smart card
An electrostatic capacitance detection device, for detecting electrostatic capacitance that changes in accordance with a distance from a target object to read surface contours of the target object,...
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7327622 |
Semiconductor device
A semiconductor device includes: a first sense amplifier; a first bit line coupled to the first sense amplifier; a second bit line disposed next to the first bit line and electrically coupled to a...
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7323928 |
High capacitance integrated circuits
An integrated circuit providing high equivalent capacitance ranging from a few tens of picofarads to a few nanofarads is presented. The integrated circuit includes active integrated circuit...
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7321514 |
DRAM memory cell arrangement
The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which...
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7321502 |
Non volatile data storage through dielectric breakdown
A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written...
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