Matches 651 - 700 out of 1910 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >
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6385120 Power-off state storage apparatus and method  
A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a...
6381184 Method and apparatus for rapidly testing memory devices  
A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of...
6381165 Semiconductor memory device having storage node electrodes offset from each other  
A semiconductor memory device that is capable of reducing the probability of a bridge being generated between storage node electrodes, and a mask pattern for defining the storage node electrodes,...
6377494 Semiconductor device and electronic apparatus  
A semiconductor device has a cell-plate-potential-switching circuit that comprises a switch transistor nSTr (a n-type MOS transistor) and a switch transistor pSTr (a p-type MOS transistor). One...
6377483 Semiconductor memory device having improved memory cell and bit line pitch  
Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for...
6370057 Semiconductor memory device having plate lines and precharge circuits  
A dynamic semiconductor memory device includes memory cells each having a one-transistor/one-capacitor. The memory cells are arranged at their respective intersections of bit lines and word lines....
6366489 Bi-state ferroelectric memory devices, uses and operation  
Bi-state ferroelectric-MOS (FMOS) capacitors are adapted for use in memory cells of a memory device. Bi-state ferroelectric memory cells have a bottom plate of a capacitor coupled to a first...
6366488 Ferroelectric non-volatile memory cell integrated in a semiconductor substrate  
Presented is a ferroelectric non-volatile memory cell in a semiconductor substrate that has a MOS device connected in parallel to a ferroelectric capacitor. The MOS device has first and second...
6363003 Ferroelectric memory device  
A ferroelectric memory device includes: a matrix of memory cells each including a semiconductor transistor and a ferroelectric capacitor; word lines and bit lines provided so as to intersect each...
6362502 DRAM cell circuit  
A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line....
6359825 Dynamic memory with increased access speed and reduced chip area  
A dynamic memory including a first sense amplifier circuit directly connected to a bit line of a memory cell, a second sense amplifier directly connected to a data input/output circuit, a switching...
6359830 Storage cell on integrated circuit responsive to plural frequency clocks  
An integrated circuit chip responds to clock waves having differing frequencies at different times. The chip includes a semiconductor memory cell having a write enable input terminal responsive to...
6359802 One-transistor and one-capacitor DRAM cell for logic process technology  
A memory cell including two switching devices, a bit line and a word line. The first switching device has an enable input. The second switching device is configured to store a charge, which...
6356503 Reduced latency row selection circuit and method  
A reduced latency row selection circuit and method for selecting a wordline in a memory instance. Capacitance associated with row select path is de-coupled from capacitance associated with row...
6351407 Differential one-time programmable memory cell structure in CMOS technology  
An OTP memory integrated circuit in CMOS technology, including at least two oxide capacitors forming a differential reading storage element, and a read and programming circuit in which the...
6349065 Semiconductor memory device allowing acceleration testing, and a semi-finished product for an integrated semiconductor device that allows acceleration testing  
A DRAM includes a row predecoder responsive to an multi-selection signal for activating all predecode signals independent of a row address signal, and a row decoder unit responsive to the...
6349052 DRAM cell arrangement and method for fabricating it  
A capacitor of a memory cell is produced in a depression (V) in a first substrate ( 1 ). The first substrate ( 1 ) is connected to a second substrate ( 2 ) in such a way that an insulating layer...
6347058 Sense amplifier with overdrive and regulated bitline voltage  
In many DRAM (Dynamic Random Access Memory) architectures, a sense amplifier detects and amplifies a small voltage differential between complementary bitline pairs to read from/write to a DRAM...
6347059 Integrated memory having a bit line reference voltage, and a method for producing the bit line reference voltage  
A semiconductor memory, in particular a ferroelectric semiconductor memory, has a differential write/read amplifier which is connected, via transfer transistors, to a bit line pair. The bit line...
6344990 DRAM for storing data in pairs of cells  
A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third...
6345006 Memory circuit with local isolation and pre-charge circuits  
A sense amplifier circuit that decreases the write cycle row to column time and pre-charge time by locally isolating the digit lines from the N-sense and P-sense amplifier circuits and pre-charging...
6343039 Data transfer circuit  
A data transfer circuit includes data lines for transferring data, interface input/output blocks connected to the data lines for input or output of data through the data lines, and a leakage...
6339542 Static random access memory (RAM) systems and storage cell for same  
A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit...
6339550 Soft error immune dynamic random access memory  
An alpha particle striking the cell of a DRAM bit can destroy stored charge, resulting in a single bit soft error. A DRAM architecture is described that circumvents this problem by storing every...
6337805 Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same  
A memory cell includes a charge amplifier having a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a ground lead...
6337806 Semiconductor device having data multiplexing and data masking functions  
A semiconductor device having data multiplexing and data masking functions is provided. The semiconductor device includes a dynamic random access memory (DRAM) cell array for inputting or...
6335873 Semiconductor integrated circuit device  
A semiconductor integrated circuit device is configured using a DRAM and an SRAM between which data transfer is performed by way of a data transfer circuit using data transfer bus lines. Herein,...
6333873 Semiconductor memory device with an internal voltage generating circuit  
A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for...
6331947 Non-volatile MOS RAM cell with capacitor-isolated nodes that are radiation accessible for rendering a non-permanent programmed information in the cell a non-volatile one  
A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a...
6331961 DRAM based refresh-free ternary CAM  
A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for...
6330181 Method of forming a gate device with raised channel  
A method for fabricating a gate device includes forming an elongated projection (422) on a substrate (412). The elongated projection (422) protrudes from a surrounding area (424) of the substrate...
6327173 Method for writing and reading a ferroelectric memory  
A method is described for reading and writing a ferroelectric memory. In ferroelectric memories, changes in a hysteresis curve on account of aging of the ferroelectric material are reduced or...
6324111 Semiconductor memory  
A semiconductor memory includes p-type MOS transistors (11) dispersed in one-to-one correspondence with sense amplifiers (4 -1 -4 -n ) to activate their corresponding sense amplifiers, and a...
6317358 Efficient dual port DRAM cell using SOI technology  
A dual port memory cell having reduced architecture utilizing silicon on insulator is provided. Each storage capacitor has respective access transistors, for connecting the storage capacitor to two...
6317357 Vertical bipolar read access for low voltage memory cell  
A memory device is described which has an n-channel FET access transistor coupled between a memory cell and a data communication line. An NPN bipolar access transistor is also coupled between the...
6314017 Semiconductor memory device  
A semiconductor memory device comprising a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line, a read...
6314018 Integrated memory with at least two plate segments  
One electrode of each storage capacitor C of the memory cells MC is connected via the associated memory transistor T to one of the bit lines BLi and another electrode is connected to one of the...
6310797 Drive method for FeRAM memory cell and drive device for the memory cell  
A method is disclosed for driving a memory cell formed of a ferroelectric capacitor FC and a transistor Tr. While maintaining a cell plate line CP at an intermediate voltage level Vcc/2 of a power...
6309924 Method of forming self-limiting polysilicon LOCOS for DRAM cell  
A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is...
6310813 Methods and apparatus for bypassing refreshing of selected portions of DRAM devices  
Refreshing of a portion of a DRAM device is bypassed when carrying out a refreshing operation on the DRAM device. By bypassing the refreshing of a portion of the DRAM device when carrying out a...
6307771 Integrated memory having 2-transistor/2-capacitor memory cells  
An integrated memory includes word lines and bit lines intersecting each other at crossover points. The bit lines are combined into bit line pairs and the bit line pairs are interleaved by having...
6304478 Layout for a semiconductor memory  
The invention pertains to a layout for a semiconductor memory with multiple memory cells. The layout according to this invention takes into account the "design rules" specified by the manufacturing...
6301175 Memory device with single-ended sensing and low voltage pre-charge  
A dynamic memory has one digit line in place of two digit lines for sensing charges stored on memory cell capacitors. The memory device uses a low digit line pre-charge voltage to allow for a low...
6301145 Ferroelectric memory and method for accessing same  
A ferroelectric memory capable of guaranteeing stable access without destruction of data while maintaining a very small cell size, and a method for accessing the same, which independently selects a...
6297999 Semiconductor memory device and method for setting stress voltage  
The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs...
6298003 Boost circuit of DRAM with variable loading  
A boost circuit for driving word lines in a memory device, comprises: a delaying module for delaying signal to turn on a refresh cycle of the boost circuit; a precharge timing controlling module...
6295240 Controlling a sense amplifier  
A semiconductor memory device arrangement that provides improved sensitivity of a sense amplifier that reads data from a memory cell. This sensitivity increase is accomplished by increasing a...
6288952 System for improved memory cell access  
A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across...
6288931 Ferroelectric memory device having cell groups containing capacitors commonly coupled to transistor  
A ferroelectric memory device includes: a plurality of cell groups, wherein each cell group includes a transistor and at least two ferroelectric capacitors commonly coupled to the transistor; at...
6288927 Semiconductor memory device with column gate and equalizer circuitry  
A semiconductor memory device includes a semiconductor substrate and a plurality of element regions formed in the semiconductor, wherein at least one column gate and at least one equalizer are...
Matches 651 - 700 out of 1910 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >