Matches 501 - 550 out of 1910 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >
Match Document Document Title
6687151 Voltage generation circuit for selectively generating high and negative voltages on one node  
An output node NO is, on one hand, connected through a PMOS transistor TP 1 and an NMOS transistor TN 1 to ground, and on the other hand, connected through a PMOS transistor TP 2 and an NMOS...
6680864 Method for reading a vertical gain cell and array for a dynamic random access memory  
A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical...
6680499 Semiconductor device and method of manufacturing the same  
Provided are a semiconductor memory device that permits increasing the degree of integration without decreasing the capacitance of the capacitor included in a memory cell, and a method of...
6677199 Structure for preventing salicide bridging and method thereof  
A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the...
6678186 Row decoded biasing of sense amplifier for improved one's margin  
A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals...
6671197 Contest addressable memory (CAM) with tri-state inverters for data storage  
A memory device includes an array of memory cells. When in use, each cell can store a charge representing a binary digit of data. Data lines are connected to the memory cells. The data lines are...
6671199 DATA STORAGE METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE EQUIPPED WITH MANY OF THE SEMICONDUCTOR INTEGRATED CIRCUITS, AND ELECTRONIC APPARATUS USING THE SEMICONDUCTOR DEVICE  
In a data storage method for memory cells 1, 2 that compose a semiconductor integrated circuit, a power supply potential VDD or a potential VL that is lowered from the power supply potential VDD...
6667898 Method for measuring bias voltage of sense amplifier in memory device  
A method for measuring a bias voltage of plural sense amplifiers in a memory device is provided. The method includes the steps of: selecting the plural sense amplifiers as a measurement area,...
6665206 Array architecture for depletion mode ferroelectric memory devices  
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments have an array architecture such that two memory cells sharing the same bit line also...
6661732 Memory system having reduced powder data refresh  
The present invention discloses a memory whose power consumption for refresh is reduced to such a level as that of medium and low speed devices, such as SRAM, in its data retention mode. A...
6661701 Three-transistor DRAM cell and associated fabrication method  
The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer...
6661699 Random access memory cell having double-gate access transistor for reduced leakage current  
A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( 300 ) includes a storage capacitor ( 304 ) and a pass transistor ( 302 ). The pass transistor ( 302 )...
6661702 Double gate DRAM memory cell having reduced leakage current  
A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( 300 ) includes a storage capacitor ( 304 ) and a pass transistor ( 302 ). The pass transistor ( 302 )...
6661700 Semiconductor memory device  
A semiconductor memory device of the present invention has a memory array structure wherein a plurality of word lines and a plurality of bit lines for selecting a predetermined memory cell are...
6650569 Boost device for nonvolatile memories with an integrated stand-by charge pump  
The boost device comprises a charge pump circuit having an input and a main output between which an input stage, an intermediate stage and a main output stage are cascade connected. The charge pump...
6646905 Ferroelectric storage device  
A ferroelectric storage device having 2Tr-2C cell structure or 1Tr-1C cell structure, which can be assessed by a screening test. In the test, a regulated reference voltage is supplied from an...
6646944 Semiconductor memory device  
In a memory sub-block, a refresh activation instruction signal from a main control circuit is taken in by a de-multiplexer in a local control circuit under a predetermined condition and refreshing...
6646908 Integrated memory chip with a dynamic memory  
The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the...
6643205 Apparatus and method for refresh and data input device in SRAM having storage capacitor cell  
An apparatus for a refresh and a data input device in the SRAM having a storage capacitor cell comprises an internal clock generator for generating and outputting two internal clock signals having...
6639824 Memory architecture  
An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output...
6639846 Method and circuit configuration for a memory for reducing parasitic coupling capacitances  
A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two adjacent bit lines, in particular...
6639825 Data memory  
The data memory device has a plurality of memory cells for storing data which are represented by a first physical value of the storing memory elements, especially their conductivity or charge. The...
6639823 Ferroelectric memory device and method of driving the same  
A ferroelectric memory device includes a memory cell array in which a plurality of memory cells having at least one ferroelectric capacitor are arranged. Three or more values of data (Pr( 0 ), P 1...
6635933 Structure of a capacitor section of a dynamic random-access memory  
Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the...
6636435 Ferroelectric memory cell array and method of storing data using the same  
The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality...
6625064 Fast, low power, write scheme for memory circuits using pulsed off isolation device  
A circuit, for controlling a write operation during which data from data lines is written to a memory cell, is used with a memory cell of the type that is connected to a row line and a first column...
6618296 Charge pump with controlled charge current  
A charge pump circuit is configured for suitably controlling the charging current in the charge pump capacitors. The charge pump circuit comprises an input current controlling circuit comprising a...
6611448 Ferroelectric memory and method for reading the same  
A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a bit line and sense amplifier. The gain depends on a capacitance ratio rather than the...
6608772 Low-power semiconductor memory device  
Sense amplifiers are alternately disposed on both sides of bit line pairs, switch circuits are provided so as to selectively connect two bit lines to a sense amplifier, and connection between a...
6608340 Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication  
A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main...
6600680 Circuit configuration and method for determining a time constant of a storage capacitor of a memory cell in a semiconductor memory  
A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled...
6600674 Ferroelectric memory device including a controller  
Bit lines to which memory cells having a capacitor formed of a ferroelectric substance are connected are each divided into a plurality of line segments. These line segments can be electrically...
6597599 Semiconductor memory  
In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate...
6594188 Integrated memory having a cell array and charge equalization devices, and method for the accelerated writing of a datum to the integrated memory  
An integrated memory having a memory cell array with addressable column lines and addressable row lines is described. The memory further has a charge equalization device for charge equalization on...
6590799 On-chip charge distribution measurement circuit  
A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and...
6590798 Apparatus and methods for imprint reduction for ferroelectric memory cell  
Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory cell, a toggle bit is sensed from a...
6587366 Ferroelectric memory device and method for operating ferroelectric memory device  
A ferroelectric memory device capable of high-speed drive having a word line to which a plurality of memory cells is connected, wherein the plurality of memory cells is divided into at least two...
6587368 Non-volatile memory circuit  
A memory circuit has a volatile memory portion and two ferroelectric capacitors. The volatile memory portion has two internal nodes and the ferroelectric capacitors are coupled in series to form a...
6586787 Single electron device  
A single electron device. Fabricated from nanoparticle derivatives, particularly from Au and fullerene nanoparticle derivatives, the device reduces thermal fluctuation in the nanoparticle array and...
6584010 Selective device coupling  
Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective...
6584009 Memory integrated circuit with improved reliability  
A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare...
6580634 Data memory device  
A data memory device is provided that is capable of reading data accurately even if the reading action is repeated. Respective output ends of memory cells D 0 -D 7 and input ends on one side of...
6577548 Self timing interlock circuit for embedded DRAM  
A method and circuit for a self timed DRAM. The circuit includes interlock circuits coupled to an extension of the DRAM. The extension does not store “real” data but mimics the operations of...
6574134 Non-volatile ferroelectric capacitor memory circuit having nondestructive read capability  
A non-destructive ferroelectric capacitor-based memory circuit has a plurality of word lines located in parallel to each other. A plurality of bit lines is located across the word lines and a...
6573613 Semiconductor memory device having cell plate electrodes allowing independent power supply for each redundant replacement unit  
A word line and a cell plate electrode line are formed at a common interconnection layer. A redundant replacement unit for a faulty row is set corresponding to the cell plate electrode line. For...
6574140 Low voltage single supply CMOS electrically erasable read-only memory  
P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps...
6574131 Depletion mode ferroelectric memory device and method of writing to and reading from the same  
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Such memory cells find use in non-volatile memory devices as well as other electronic systems having...
6573543 Reset apparatus, semiconductor IC apparatus, and semiconductor memory apparatus  
A reset device detects a rise of a supply voltage to start outputting a reset signal. The reset device includes a voltage detection circuit for detecting the supply voltage. The voltage detection...
6574132 Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits  
The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage...
6574136 Reduced leakage memory cell  
A random access memory cell ( 10 ) includes a first conductor line ( 12 ) and a second conductor line ( 14 ). A native device ( 16 ) is arranged to store charge. A high voltage threshold transistor...
Matches 501 - 550 out of 1910 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >