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6781864 System and method for inhibiting imprinting of capacitor structures of a memory  
A system and method for inhibiting the imprinting of capacitor structures employed by memory cells by occasionally changing charge states of the capacitors to a complementary charge state.
6778424 Semiconductor memory device and method of manufacturing the same  
A semiconductor memory device having MIS transistors to constitute memory cells (MC), each of the MIS transistors including a semiconductor layer ( 12 ), a source region ( 15 ) formed in the...
6778435 Memory architecture for TCCT-based memory cells  
A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to...
6775177 Semiconductor memory device switchable to twin memory cell configuration  
A row address decoder of a semiconductor memory device generates internal row address signals RAD< 0:11> and /RAD< 0:11 > by switching most significant bit and least significant bit of...
6775175 Blowable memory device and method of blowing such a memory  
A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that...
6775174 Memory architecture for micromirror cell  
A one transistor one capacitor micromirror with DRAM memory cell built around a large polysilicon-to-substrate capacitor which is not susceptible to recombination of photo-generated carriers caused...
6771527 Integrated DRAM memory component  
An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged...
6771531 Memory device and memory system using same  
A memory device including a cross point type ferroelectric memory and a randomly accessible write back type cache memory, where the cross point type ferroelectric memory is accessed via a second...
6768687 Memory array  
An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and...
6769041 Method and apparatus for providing bimodal voltage references for differential signaling  
According to an embodiment of the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices....
6768667 Semiconductor memory device  
A DRAM memory cell having an isolation transistor formed from a bipolar transistor.
6762968 Semiconductor memory device having a small-sized memory chip and a decreased power-supply noise  
The bit line overdrive circuit of the present invention comprises a VBLH potential generation circuit generating a bit line final potential relative to a VBLH power supply line for driving a sense...
6762966 Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to DRAM MOSFET array transistor  
An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The...
6760248 Voltage regulator with distributed output transistor  
A memory device and method of manufacturing thereof having a voltage regulator with distributed output transistor. A novel approach for the bitline high voltage (V BLH ) generation is used to save...
6757186 Method and logic decision device for generating ferro-electric capacitor reference voltage  
A method of producing a reference voltage through a ferro-electric capacitor. A ferro-electric capacitor for determining logic level of data is charged so that the amount of electric charges within...
6754110 Evaluation circuit for a DRAM  
A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling...
6754125 Method and device for refreshing reference cells  
Reference cells are refreshed in a non-volatile memory that includes a plurality of memory cells. A selected reference cell and a non-used memory cell are read simultaneously, and a signal read...
6747890 Gain cell structure with deep trench capacitor  
Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor...
6744657 Read only data bus and write only data bus forming in different layer metals  
A semiconductor memory device that enables data buses to operate at high speed by reducing wiring capacitance and interference noise between data bus lines is provided. A semiconductor memory...
6744676 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same  
A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is...
6744658 Semiconductor memory device capable of holding write data for long time  
A semiconductor memory device includes memory cells. Each memory cell includes three P-channel MOS transistors. The first P-channel MOS transistor is connected between a bit line and a node, and...
6741491 Integrated dynamic memory, and method for operating the integrated dynamic memory  
An integrated dynamic memory has word lines and bit lines as well as at least one global bit line, which is disposed in the memory cell array in the same sense as the bit lines. A voltage amplifier...
6738282 Random access memory and method for controlling operations of reading, writing, and refreshing data of the same  
The disclosure is a method of controlling operations in a static random access memory employing twin cells. After a wordline coupled to first and second cell transistors is conductive, a voltage...
6738303 Technique for sensing the state of a magneto-resistive random access memory  
The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the...
6735141 Semiconductor memory device having an SRAM and a DRAM on a single chip  
A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input...
6735109 Uni-transistor random access memory device and control method thereof  
An SRAM device according to the present invention includes at least one twin cell to which first and second bitlines are coupled. The first and second bitlines are precharged to a power supply...
6735106 Accelerated fatigue testing  
A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the...
6731529 Variable capacitances for memory cells within a cell group  
A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the capacitances of the capacitors advantageously...
6731556 DRAM with bias sensing  
A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line....
6731554 2T2C signal margin test mode using resistive element  
The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime...
6728152 Sense amplifier for reduction of access device leakage  
A sense amplifier circuit includes first and second amplifier circuits. The first amplifier circuit includes a pair of cross-coupled transistors of a first channel type (e.g., N-channel FETs), and...
6728128 Dummy cell structure for 1T1C FeRAM cell array  
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate...
6724645 Method and apparatus for shortening read operations in destructive read memories  
An apparatus and method for shortening the read operation (typically the longest operation) in a destructive read memory is disclosed. The rewrite step is separated from the read operation and...
6724667 Data memory with redundant memory cells used for buffering a supply voltage  
A data memory for storing data, having a memory cell array ( 2 ), which comprises a large number of memory cells ( 3 ), each of which can be addressed by means of a memory cell select transistor (...
6721214 Drive circuit and control method  
A circuit has a control signal input, a control signal output, a delay element for generating a delay duration, and a control logic circuit. The latter controls the delay element and switches a...
6721225 Semiconductor memory device with activation of a burst refresh when a long cycle is detected  
A semiconductor memory device according to the invention has an active state where data can be read and written and a standby state where the data are retained. It has a memory cell array including...
6717838 Semiconductor storage device with ferroelectric capacitor and read transistor having gate communicating with bit line  
M memory cells (MC) in each of which a ferroelectric capacitor (FC) and a selector transistor (CTR) are connected in series are connected in parallel between a drive line (DL) and a bit line (BL)....
6714436 Write operation for capacitorless RAM  
A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region ( 12 ). Data is...
6714476 Memory array with dual wordline operation  
A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the...
6711048 2-port memory device  
A 2-port memory device is provided. The 2-port memory device is necessary to be periodically refreshed to maintain the data stored in cells of the memory device. The memory device can be accessed...
6711050 Semiconductor memory  
A folded bitline type sense amplifier circuit is disposed at an outer side of an end memory cell array in which 2Tr1C type cells each composed of a data storage capacitor, an A port access...
6707706 Semiconductor memory device and method for manufacturing the same  
A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a...
6707730 Semiconductor memory device with efficient and reliable redundancy processing  
A semiconductor memory device includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is...
6707705 Integrated dynamic memory device and method for operating an integrated dynamic memory  
In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the...
6704219 FeRAM memory and method for manufacturing it  
To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices...
6704221 Floating gate programmable cell array for standard CMOS  
A new floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to...
6700827 Cam circuit with error correction  
A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the...
6697279 Ferroelectric read/write memory with series-connected memory cells (CFRAM)  
The memory device has series-connected ferroelectric memory cells in which a series circuit composed of a resistor and/or of a transistor for the ferroelectric capacitor of a respective memory cell...
6687150 Reference voltage generation for memory circuits  
An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference...
6687177 Reference cells with integration capacitor  
A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint...
Matches 451 - 500 out of 1910 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >