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7609572 |
Semiconductor memory device
In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed...
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7603513 |
ROM-based multiple match circuit
A ROM-based multiple match system and method for producing a match signal in an addressable memory system are described. In various embodiments of the present invention, a ROM is used to generate...
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7599230 |
Semiconductor memory apparatus and method of driving the same
A semiconductor memory apparatus includes: a cell region having a plurality of unit cells each of which has a switching MOS transistor for transferring data. A peripheral circuit unit accesses data...
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7589990 |
Semiconductor ROM device and manufacturing method thereof
The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple...
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7577013 |
Storage units and register file using the same
A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a...
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7573749 |
Counteracting overtunneling in nonvolatile memory cells
Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge,...
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7573077 |
Thyristor-based semiconductor memory device with back-gate bias
In accordance with an embodiment of the present invention, a thyristor-based semiconductor memory device may comprise an array of thyristor-based memory formed in an SOI wafer. A supporting...
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7567450 |
Low power ROM
A low power ROM includes a plurality of ROM core groups coupled between a plurality of word lines and bit lines, a word line decoder for selecting a desired word line of the plurality of word...
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7561457 |
Select transistor using buried bit line from core
A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The...
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7545019 |
Integrated circuit including logic portion and memory portion
An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and...
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7535788 |
Dynamic power control for expanding SRAM write margin
A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a...
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7522445 |
Semiconductor memory
A semiconductor memory having a plurality of static random access memory cells, word lines, first and second bit lines orthogonal to the word lines, and threshold voltage control lines parallel to...
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7522443 |
Flat-cell read-only memory structure
The integrated circuit memory comprises a memory array including a plurality of memory cells in rows and columns, the memory array being divided into a plurality of blocks of the memory cells. Each...
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7518177 |
Semiconductor storage device
A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a...
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7505326 |
Programming pulse generator
A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a...
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7483310 |
System and method for providing high endurance low cost CMOS compatible EEPROM devices
A system and method are disclosed for providing EEPROM devices that combine the high endurance features of complex and expensive EEPROM devices and the low manufacturing costs of CMOS compatible...
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7480166 |
Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell
A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit...
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7471541 |
Memory transistor gate oxide stress release and improved reliability
Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are...
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7471540 |
Non-volatile semiconductor memory based on enhanced gate oxide breakdown
A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate...
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7466618 |
Current limiting antifuse programming path
Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear...
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7460424 |
Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase
A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so...
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7453718 |
Digital data apparatuses and digital data operational methods
Digital data apparatuses and digital data operational methods are described. According to one embodiment, a digital data apparatus includes a semiconductive substrate comprising a node location...
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7447074 |
Read-only memory
An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different...
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7447054 |
NBTI-resilient memory cells with NAND gates
An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates...
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7447053 |
Memory device and method for operating such a memory device
A memory device and method for operating a memory device is described. In one embodiment, the memory device has at least one memory cell including an active material, a current supply line, and a...
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7443706 |
High-performance memory and related method
In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the...
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7436690 |
Flat cell read only memory using common contacts for bit lines and virtual ground lines
In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line...
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7414909 |
Nonvolatile semiconductor memory
There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each...
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7411808 |
Method for reading ROM cell
A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control...
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7408806 |
Memory array architecture for a memory device and method of operating the memory array architecture
A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having...
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7379318 |
Semiconductor integrated circuit device and method for manufacturing the same
A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate....
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7376000 |
Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets
Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable...
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7372716 |
Memory having CBRAM memory cells and method
A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming...
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7359230 |
Nonvolatile memory device
Provided is a nonvolatile memory device including: a storage element; a switching element electrically connected to the storage element; and a plurality of lead wirings electrically connected to...
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7359226 |
Transistor, memory cell array and method for forming and operating a memory device
A substrate forming an array of vertical transistor cells for selecting one of a plurality of memory cells and wherein each memory cell couples a transistor to a bit line via a memory element and...
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7355890 |
Content addressable memory (CAM) devices having NAND-type compare circuits
Content addressable memory (CAM) devices have CAM cells therein that are electrically coupled to a NAND-type compare circuit. This NAND-type compare circuit is responsive to a first operand (K)...
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7355876 |
Memory array circuit with two-bit memory cells
A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through...
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7333386 |
Extraction of a binary code based on physical parameters of an integrated circuit through programming resistors
An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between...
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7333356 |
One-time programmable memory devices
The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection...
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7321514 |
DRAM memory cell arrangement
The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which...
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7321501 |
Method for trimming programmable resistor to predetermined resistance
A programmable resistor is an e-fuse connecting to a source/drain of a MOS transistor. A voltage is provided to the gate of the MOS transistor to partially blow the programmable resistor. Following...
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7319627 |
Memory device
A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit...
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7319610 |
MTP storage medium and access algorithm method with traditional OTP
A method for performing multi-programmable function with one-time programmable (OTP) memories includes: generating a newest word in a OTP memory array; receive a word-to-be-record; comparing the...
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7319608 |
Non-volatile content addressable memory using phase-change-material memory elements
A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first...
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7310266 |
Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode
A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a...
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7307873 |
Memory with five-transistor bit cells and associated control circuit
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory...
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7307865 |
Integrated read-only memory, method for operating said read-only memory and corresponding production method
An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer...
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7304879 |
Non-volatile memory element capable of storing irreversible complementary data
A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the memory cell exhibiting a first...
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7298640 |
1T1R resistive memory array with chained structure
A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile...
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7295486 |
Memory and driving method therefor
A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th...
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