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7639559 Semiconductor memory device  
In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current....
7589990 Semiconductor ROM device and manufacturing method thereof  
The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple...
7545019 Integrated circuit including logic portion and memory portion  
An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and...
7518900 Memory  
A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity...
7480166 Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell  
A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit...
7433224 System and method for forcing an SRAM into a known state during power-up  
There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of...
7411808 Method for reading ROM cell  
A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control...
7394088 Thermally contained/insulated phase change memory device and method (combined)  
A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed...
7245000 Electrically isolated pillars in active devices  
A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third...
7219271 Memory device and method for redundancy/self-repair  
The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of...
7215563 Multi-layered memory cell structure  
A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available...
7212432 Resistive memory cell random access memory device and method of fabrication  
A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a...
7131033 Substrate configurable JTAG ID scheme  
A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port...
7110278 Crosspoint memory array utilizing one time programmable antifuse cells  
Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.
7015553 Compact mask programmable ROM  
A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality of bit lines, and a plurality of MOS-type and diffusion-type memory cells...
6943395 Phase random access memory with high density  
A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors....
6940770 Method for precharging word and bit lines for selecting memory cells within a memory array  
The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated...
6922356 Method of operation for a programmable circuit  
A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold...
6912146 Using an MOS select gate for a phase change memory  
An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.
6867995 Read only memory configuration to reduce capacitance effect between numbers of bit lines  
A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB 1 (n) to SB 4 (n), selection switches MB 1 (n) to MB 4 (n), and...
6865100 6F2 architecture ROM embedded DRAM  
A read only memory (ROM) embedded dynamic random access memory (DRAM) has a 6F 2 architecture and uses isolation gates as hard shorting connections for ground or supply voltage connections to...
6848071 Method and apparatus for updating an error-correcting code during a partial line store  
One embodiment of the present invention provides a system that updates an error-correcting code for a line when only a portion of the line is updated during a store operation. The system operates...
6822888 Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric  
A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into...
6809948 Mask programmable read-only memory (ROM) cell  
A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate...
6781902 Semiconductor memory device and method of testing short circuits between word lines and bit lines  
The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short...
6750101 Method of manufacturing self-aligned, programmable phase change memory  
A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process...
6716698 Virtual ground silicide bit line process for floating gate flash memory  
One aspect of the invention relates to a virtual ground array floating gate flash memory device with salicided buried bit lines. The bit lines are implanted and salicided after formation of memory...
6674661 Dense metal programmable ROM with the terminals of a programmed memory transistor being shorted together  
A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are...
6661691 Interconnection structure and methods  
Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of...
6650579 Semiconductor device having test and read modes and protection such that ROM data reading is prevented in the test mode  
A semiconductor device having a test mode and a read mode is provided. This semiconductor device includes a ROM and a control circuit. When a predetermined condition is satisfied, the control...
6636434 Multibit memory point memory  
A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column...
6624485 Three-dimensional, mask-programmed read only memory  
A 3-dimensional read only memory includes vertically stacked layers of memory cells. Each of the memory cells includes a mask programmed insulating layer, a pair of diode components, and a pair of...
6602671 Semiconductor nanocrystals for inventory control  
A novel encoding system, compositions for use therein and methods for determining the source, location and/or identity of a particular item or component of interest is provided. In particular, the...
6600673 Compilable writeable read only memory (ROM) built with register arrays  
A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and...
6587394 Programmable address logic for solid state diode-based memory  
A level of a solid state memory device includes main memory and address logic. The address logic includes first and second groups of address elements. Current-carrying capability of the first group...
6587387 Device and method for testing mask ROM for bitline to bitline isolation leakage  
A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate...
6579760 Self-aligned, programmable phase change memory  
A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process...
6570235 Cells array of mask read only memory  
A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells...
6496423 Chip ID register configuration  
A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the...
6487129 Semiconductor apparatus  
To correct a software bug in a microcomputer for use in various electric apparatus having a mask ROM mounted therein without correcting the mask ROM. When there is a bug in a first data, a...
6477083 Select transistor architecture for a virtual ground non-volatile memory cell array  
A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to...
6473327 Semiconductor memory having a pair of bank select drivers driving each bank select line  
A semiconductor memory comprises a memory cell array having a plurality of rows and a plurality of columns, a plurality of word lines each connected to a gate of memory cells of a corresponding row...
6442058 Control circuit and semiconductor device including same  
A control circuit comprises an external command recognition section for recognizing an external command, the external command being an operation command input from outside the control circuit, an...
6434433 External components for a microprocessor system for control of plural control elements and operating method  
The external intelligent component ( 3 ) connected with a microprocessor system ( 2 ) is described for essentially automatic control of a control element ( 1 ) without burdening the microprocessor...
6385074 Integrated circuit structure including three-dimensional memory array  
An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read...
6347047 Mask ROM semiconductor memory device capable of synchronizing the activation of the sense amplifier and of the word line  
A semiconductor memory device is provided with a memory cell array, a sense circuit which activates main bit lines in the memory cell array, a buffer which generates an activating signal which...
6304480 Read only memory integrated semiconductor device  
A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is...
6282114 Low consumption ROM  
A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the...
6218695 Area efficient column select circuitry for 2-bit non-volatile memory cells  
A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits...
6205075 Semiconductor memory device capable of reducing the effect of crosstalk noise between main bit lines and virtual main grounding lines  
This semiconductor memory device is provided with a plurality of main bit lines; a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the...
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