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7545382 |
Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation
A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation....
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7522170 |
Graphics system interface
An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the...
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7397477 |
Memory system having multiple address allocation formats and method for use thereof
A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded...
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7388588 |
Programmable graphics processing engine
A fully programmable graphics processing engine is provided. The graphics processing engine includes three independent, programmable processors that run independent sets of instructions from...
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RE40326 |
Single chip frame buffer and graphics accelerator
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data,...
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7106340 |
Method for controlling the access to a storage device and a corresponding computer program
A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device...
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7091981 |
Data bus compressing apparatus
A bus compression apparatus for compressing data is provided to suppress an EMI signal and to simplify a data bus structure. In the apparatus, the voltage levels of the digital output signals are...
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7073035 |
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory...
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7032083 |
Glitch-free memory address decoding circuits and methods and memory subsystems using the same
Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received...
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6985155 |
Memory device and image processing apparatus using same
A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real...
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6975324 |
Video and graphics system with a video transport processor
A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for...
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6937247 |
Memory control device and method
A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode...
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6831654 |
Data processing system
A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in...
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6825841 |
Granularity memory column access
A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially...
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6801988 |
Data buffer for block unit data transfer to SDRAM
An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put...
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6593932 |
System for implementing a graphic address remapping table as a virtual register file in system memory
A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references a...
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6538656 |
Video and graphics system with a data transport processor
A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The...
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6445394 |
Serialized mapped memory configuration for a video graphics chip
A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other...
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6421058 |
Graphics command stream for calling a display object in a graphics system
An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the...
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6362824 |
System-wide texture offset addressing with page residence indicators for improved performance
A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons...
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6278467 |
Display memory control apparatus
The present invention relates to a display memory control apparatus which can shorten a waiting time in making an access to a VRAM from a CPU without making large a circuit scale and causing an...
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6104418 |
Method and system for improved memory interface during image rendering
Aspects for increasing efficiency of memory accesses during graphics rendering are provided. A preferred method aspect includes providing a plurality of memory banks for data, and decoding input...
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6028613 |
Method and apparatus for programming a graphics subsystem register set
A graphics system includes a graphics processor for rendering graphics primitives with a display list. A host processor generates a display list which includes a command format for loading the...
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6020902 |
Image data storing method and image data storing device
An image data storing device capable of solving a problem involved in a conventional device in that an increasing number of memory bus lines are required which are used for simultaneously reading...
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5999197 |
Synchronized data processing system and image processing system
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules...
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5999200 |
Method and apparatus for automatically controlling the destination of a graphics command in a register file
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for...
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5860076 |
48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses
A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address...
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5829007 |
Technique for implementing a swing buffer in a memory array
A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream...
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5796413 |
Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering
An apparatus and method are disclosed for buffering graphics commands in a video graphics system, and for implementing graphics macro commands. The invention makes use of off-screen portions of...
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5787311 |
Integrated circuit multiport memory having serial access bit mask register and method for writing in the multiport memory
An integrated circuit (IC) architecture includes a bit mask register (BMR) and a serial access memory (SAM) which share address decode and clock circuitry within a multiport random access memory...
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5784072 |
Oscillation device, display data processing device, matrix-type display device, oscillation signal generation method, and display data processing method
An oscillation device and a display data processing device adjust variables such as the duty ratio of the oscillation frequency, and control autonomously timings between components such as...
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5774135 |
Non-contiguous memory location addressing scheme
A processing system and method is disclosed to access non-contiguous memory locations within a memory block. An address is generated that has a first group of bits and a second group of bits. The...
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5727190 |
Method and system for the acceleration of graphics images in a multiprocessor or preemptive processing computer system
A method and system for accelerating graphics images in a computer system comprises encoding a first value information into an address signal from a CPU within the computer system and then encoding...
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5703616 |
Display driving device
A display data memory which is provided in a segment driver for driving a liquid crystal display panel comprises a plurality of memories. Since the common Y address is provided to all the memories,...
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5696940 |
Apparatus and method for sharing first-in first-out memory space between two streams of data
A random access memory (RAM) device that allocates memory cells to first-in first-out (FIFO) memory. The RAM device has an array of addressable memory cells that are selected by row and column...
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5668941 |
Optimum implementation of X-Y clipping on pixel boundary
A method and apparatus for improving performance of bit block transfers in display controllers during clipping functions without significantly increasing gate count. In a clipping function,...
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5638533 |
Method and apparatus for providing data to a parallel processing array
A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data...
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5634034 |
Enhanced processor buffered interface for multiprocess systems
An Enhanced Processor Buffered Interface (22c) for use in a multiprocessor system (10). The Enhanced Processor Buffered Interface executes an Atomic Fetch and Add operation for maintaining...
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5539874 |
Cache memory device for storing image data
A cache memory device stores image data which are arranged corresponding to address data having first and second two-dimensional coordinate data. The image data are divided into a plurality of...
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5530792 |
Data processing apparatus utilizing CPU
An information processing apparatus, or an image recording apparatus, utilizing a CPU and a memory and capable of improving the throughput of data processing is disclosed. When the CPU does not...
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5434969 |
Video display system using memory with a register arranged to present an entire pixel at once to the display
In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped...
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5434589 |
TFT LCD display control system for displaying data upon detection of VRAM write access
An electronic apparatus having a TFT LCD includes a detector for detecting whether or not display data in a video RAM is rewritten. When the rewrite operation of display data is detected, a display...
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5388208 |
Gerbil wheel memory
A display memory system consisting of a controller and a display memory that has a read display memory cycle time that is a non-integer multiple of the write display memory update rate. The display...
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5374940 |
System for operating a plurality of graphics displays from a single computer
Multiple video boards of the general purpose type (e.g. EGA or VGA boards) and their associated monitors are operated by a single computer of the personal computer type, without modification of the...
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5353120 |
Video field memory device for multi-broadcasting system and manufacturing method therefor
A video field memory device for multi-broadcasting system employs upper and lower half memory cell arrays for storing a video signal according to the largest scanning bit and the largest scanning...
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5333259 |
Graphic information processing system having a RISC CPU for displaying information in a window
A computer related system including a reduced instruction set computer (RISC) central processing unit for effectively processing a data bottleneck phenomenon due to a great deal of data on a bus...
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5285323 |
Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of...
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5233331 |
Inking buffer for flat-panel display controllers
An intelligent subsystem separately supports inking functions in order to allow stroke-ignorant software to be supported in a stylus driven environment. This subsystem thus provides the inking...
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5161220 |
Data write control circuit having word length conversion function
A rotation controller performs bit rotation in units of 2 bits for 8-bit data supplied from a common data bus in accordance with a mode selection signal from a mode selector and a column selection...
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5062057 |
Computer display controller with reconfigurable frame buffer memory
A computer display controller (50) cooperates with a host microprocessor (18) to direct display data to a frame buffer memory (16) in accordance with a selected one of multiple frame buffer memory...
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