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8736621 System and method for configuring a display pipeline  
Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support...
8723878 Display device integrated circuit (DDI) with adaptive memory control and adaptive memory control method for DDI  
A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by...
8704840 Memory system having multiple address allocation formats and method for use thereof  
A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format...
8581915 System and method for configuring a display pipeline using a network  
Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support...
RE44589 Single chip frame buffer and graphics accelerator  
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data,...
8493400 Memory device and memory control for controlling the same  
A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which...
8477146 Processing rasterized data  
Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized...
8259121 System and method for processing data using a network  
Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support...
8154947 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
8139048 Method of raising resolution in locating on a micro dotmap  
While a plurality of encoding blocks included in a micro dotmap are used for marking coordinates and locating a frame center on a displaying medium, a resolution of locating the frame center is...
7999820 Methods and systems for reusing memory addresses in a graphics system  
Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets...
7990391 Memory system having multiple address allocation formats and method for use thereof  
A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format...
7952589 Data processing apparatus and method thereof  
A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the...
7944452 Methods and systems for reusing memory addresses in a graphics system  
Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets...
7859541 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation  
A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation....
RE41565 Single chip frame buffer and graphics accelerator  
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data,...
7545382 Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation  
A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation....
7522170 Graphics system interface  
An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing...
7397477 Memory system having multiple address allocation formats and method for use thereof  
A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are...
7388588 Programmable graphics processing engine  
A fully programmable graphics processing engine is provided. The graphics processing engine includes three independent, programmable processors that run independent sets of instructions from...
RE40326 Single chip frame buffer and graphics accelerator  
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data,...
7106340 Method for controlling the access to a storage device and a corresponding computer program  
A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device...
7091981 Data bus compressing apparatus  
A bus compression apparatus for compressing data is provided to suppress an EMI signal and to simplify a data bus structure. In the apparatus, the voltage levels of the digital output signals are...
7073035 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules  
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory...
7032083 Glitch-free memory address decoding circuits and methods and memory subsystems using the same  
Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received...
6985155 Memory device and image processing apparatus using same  
A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real...
6975324 Video and graphics system with a video transport processor  
A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for...
6937247 Memory control device and method  
A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode...
6831654 Data processing system  
A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in...
6825841 Granularity memory column access  
A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially...
6801988 Data buffer for block unit data transfer to SDRAM  
An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put...
6593932 System for implementing a graphic address remapping table as a virtual register file in system memory  
A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references...
6538656 Video and graphics system with a data transport processor  
A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them....
6445394 Serialized mapped memory configuration for a video graphics chip  
A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other...
6421058 Graphics command stream for calling a display object in a graphics system  
An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing...
6362824 System-wide texture offset addressing with page residence indicators for improved performance  
A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons...
6278467 Display memory control apparatus  
The present invention relates to a display memory control apparatus which can shorten a waiting time in making an access to a VRAM from a CPU without making large a circuit scale and causing an...
6104418 Method and system for improved memory interface during image rendering  
Aspects for increasing efficiency of memory accesses during graphics rendering are provided. A preferred method aspect includes providing a plurality of memory banks for data, and decoding input...
6028613 Method and apparatus for programming a graphics subsystem register set  
A graphics system includes a graphics processor for rendering graphics primitives with a display list. A host processor generates a display list which includes a command format for loading the...
6020902 Image data storing method and image data storing device  
An image data storing device capable of solving a problem involved in a conventional device in that an increasing number of memory bus lines are required which are used for simultaneously reading...
5999200 Method and apparatus for automatically controlling the destination of a graphics command in a register file  
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for...
5999197 Synchronized data processing system and image processing system  
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules...
5860076 48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses  
A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address...
5829007 Technique for implementing a swing buffer in a memory array  
A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data...
5796413 Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering  
An apparatus and method are disclosed for buffering graphics commands in a video graphics system, and for implementing graphics macro commands. The invention makes use of off-screen portions of...
5787311 Integrated circuit multiport memory having serial access bit mask register and method for writing in the multiport memory  
An integrated circuit (IC) architecture includes a bit mask register (BMR) and a serial access memory (SAM) which share address decode and clock circuitry within a multiport random access memory...
5784072 Oscillation device, display data processing device, matrix-type display device, oscillation signal generation method, and display data processing method  
An oscillation device and a display data processing device adjust variables such as the duty ratio of the oscillation frequency, and control autonomously timings between components such as...
5774135 Non-contiguous memory location addressing scheme  
A processing system and method is disclosed to access non-contiguous memory locations within a memory block. An address is generated that has a first group of bits and a second group of bits. The...
5727190 Method and system for the acceleration of graphics images in a multiprocessor or preemptive processing computer system  
A method and system for accelerating graphics images in a computer system comprises encoding a first value information into an address signal from a CPU within the computer system and then...
5703616 Display driving device  
A display data memory which is provided in a segment driver for driving a liquid crystal display panel comprises a plurality of memories. Since the common Y address is provided to all the...

Matches 1 - 50 out of 80 1 2 >