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8169444 |
Bit block transfer circuit and method thereof and color filling method
A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original...
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8156314 |
Incremental state updates
A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The...
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8139072 |
Network hardware graphics adapter compression
A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card...
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8134568 |
Frame buffer region redirection for multiple graphics adapters
A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software...
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8106917 |
Method and system for mosaic mode display of video
Methods and systems for mosaic mode display of video are disclosed. Aspects of one method may include generating video data for a plurality of video windows using a single video feeder module...
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8102401 |
Display controller operating mode using multiple data buffers
A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of...
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8063907 |
Apparatus and method for selectable hardware accelerators in a data driven architecture
A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A...
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8004523 |
Translation of register-combiner state into shader microcode
An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is...
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7978200 |
Raster-order pixel dithering
Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for...
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7928990 |
Graphics processing unit with unified vertex cache and shader register file
Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared...
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7864185 |
Register based queuing for texture requests
A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture...
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7852341 |
Method and system for patching instructions in a shader for a 3-D graphics pipeline
A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D...
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7847803 |
Method and apparatus for interleaved graphics processing
The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a...
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7821520 |
Fragment processor having dual mode register file
A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader...
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7812847 |
Method and apparatus for providing bandwidth priority
A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel...
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7788656 |
System for reducing the number of programs necessary to render an image
Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to...
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RE41523 |
Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets
A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for...
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7755634 |
System, method and computer program product for branching during programmable vertex processing
A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a...
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7742063 |
Efficient and high speed 2D data transpose engine for SOC application
An apparatus comprising a buffer circuit, a rotation circuit and a memory. The buffer may be configured to store original image data in one or more sub-matrices. The rotation circuit may be...
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7714870 |
Apparatus and method for selectable hardware accelerators in a data driven architecture
A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A...
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7697010 |
Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems
A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and...
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7659909 |
Arithmetic logic unit temporary registers
An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident...
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7639263 |
Fast filtered YUV to RGB conversion
The values of each possible component output R, G, and B may be pre-computed for all values of each possible component input Y, U, and V. Each contribution of Y, U, and V input may then be loaded...
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7623132 |
Programmable shader having register forwarding for reduced register-file bandwidth consumption
A method and apparatus of operating a shader having multiple texture or shader processing stations. That method includes feeding the output of a texture or shader processing station directly into...
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7576747 |
Display controller, electronic equipment and method for supplying image data
The display controller includes a first memory storing image data and being accessed with a sequential access operation having a shorter access time than that of a random access operation, a second...
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7565490 |
Out of order graphics L2 cache
Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that...
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7546480 |
High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow...
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7538771 |
Mail data processing method, mail server, program for mail server, terminal device and program for terminal device
A mail server extracts a character unregistered in a portable terminal from received mail data and affixes the font data of the character concerned to the mail data or inserts a reading tag...
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7515766 |
Apparatus and method for edge handling in image processing
A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute...
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7512021 |
Register configuration control device, register configuration control method, and program for implementing the method
A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives...
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7508396 |
Register-collecting mechanism, method for performing the same and pixel processing system employing the same
A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a...
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7492371 |
Hardware animation of a bouncing image
A graphics controller for animating an overlay is described. The graphics controller includes a host interface for communicating with an external processor and a plurality of registers in...
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7490208 |
Architecture for compact multi-ported register file
Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port...
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7483033 |
Storage device
A storage device comprises a plurality of memory blocks each including a plurality of cells in correspondence with a data length of image data consisting of a plurality of pixel data, wherein a...
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7466316 |
Apparatus, system, and method for distributing work to integrated heterogeneous processors
An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types...
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7456835 |
Register based queuing for texture requests
A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture...
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7446773 |
Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler
An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or...
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7436410 |
System and method for programming a controller
A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a...
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7426722 |
Program code conversion for program code referring to variable size registers
A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine...
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7409680 |
Program code conversion for a register-based program code
A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine...
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7400328 |
Complex-shaped video overlay using multi-bit row and column index registers
A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that...
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7355602 |
Surrogate stencil buffer clearing
Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil...
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7346900 |
Register-based program code conversion
A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine...
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7339592 |
Simulating multiported memories using lower port count memories
An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of...
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7333106 |
Method and apparatus for Z-buffer operations
In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory....
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7324106 |
Translation of register-combiner state into shader microcode
An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is...
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7280111 |
API communications for vertex and pixel shaders
A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided...
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7196708 |
Parallel vector processing
A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a...
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7142221 |
Display drive control device and electric device including display device
In a system including a color liquid crystal panel, a drive control device for driving the panel, and a microprocessor, the drive control device reduces the burden on the microprocessor as well as...
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7136068 |
Texture cache for a computer graphics accelerator
A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of...
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