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Match Document Document Title
8988444 System and method for configuring graphics register data and recording medium  
A system and method for configuring graphics register data and a recording medium are applied in a mobile device to store graphics operation data for displaying a picture. The system includes a...
8982033 Bidirectional shift register and image display device using the same  
A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.
8970604 State display device and display method of state display device  
A state display device capable of reducing a processing load applied to a microcomputer by performing part of a GUI process by hardware and a display method of the state display device are...
8937614 Bidirectional shift register and display device using the same  
A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or...
8933954 Register allocation for graphics processing  
In general, aspects of this disclosure describe a compiler for allocation of physical registers for storing constituent scalar values of a non-scalar value. In some example, the compiler,...
8922555 Pixel shader output map  
One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render...
8902212 Image display systems and bi-directional shift register circuits  
A bi-directional shift register circuit includes multiple stages of shift registers for generating multiple gate driving signals. At least one shift register includes an input stage circuit, an...
8860701 Control method for bi-stable displaying, timing controller, and bi-stable display device with such timing controller  
A control method for bi-stable displaying is provided, using queues for storing coordinates to achieve pipeline parallel processing on display data, thereby increasing display speed. In a...
8836709 Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline  
Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and...
8803783 Bidirectional shift register and image display device using the same  
A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom...
8803782 Bidirectional shift register and image display device using the same  
A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ╬╗th stage of unit...
8780121 Graphics render clock throttling and gating mechanism for power saving  
An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be...
8766996 Unified virtual addressed register file  
A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as...
8754893 Apparatus and method for selectable hardware accelerators  
A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A...
8704840 Memory system having multiple address allocation formats and method for use thereof  
A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format...
8681161 Multi-pass system and method supporting multiple streams of video  
Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a...
8599208 Shared readable and writeable global values in a graphics processor unit pipeline  
An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be...
8564523 Shift register and liquid crystal display having the same  
In a shift register and an LCD having the same, the shift register includes plural stages having odd stages for receiving a first clock signal and a first control signal and even stages for...
8558841 Register configuration control device, register configuration control method, and program for implementing the method  
A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives...
8462167 Memory access control circuit and image processing system  
A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and...
8379032 System and method of mapping shader variables into physical registers  
The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are...
8358312 Multi-pass system and method supporting multiple streams of video  
Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a...
8355028 Scheme for varying packing and linking in graphics systems  
A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables...
8339658 Image forming apparatus and image forming method  
An image forming apparatus including: a video memory; a load management unit that loads page data on a print image into the video memory page by page; a print engine that performs printing using...
8314803 Buffering deserialized pixel data in a graphics processor unit pipeline  
An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock...
8300058 ELUT: enhanced look-up table signal processing  
An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its...
8243069 Late Z testing for multiple render targets  
The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders....
8237726 Register allocation for message sends in graphics processing pipelines  
Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.
8232991 Z-test result reconciliation with multiple partitions  
The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders....
8228328 Early Z testing for multiple render targets  
The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders....
8223150 Translation of register-combiner state into shader microcode  
An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state...
8189007 Graphics engine and method of distributing pixel data  
A graphics engine and related method of operation are disclosed in which a pixel distributor distributes pixel data across a plurality of pixel shaders using a first approach when the presence of...
8169444 Bit block transfer circuit and method thereof and color filling method  
A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original...
8156314 Incremental state updates  
A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The...
8139072 Network hardware graphics adapter compression  
A Video Card with standard video output and a Network Ethernet port output of compressed digital video output that represents the image seen by a monitored computer user. A custom video card...
8134568 Frame buffer region redirection for multiple graphics adapters  
A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software...
8106917 Method and system for mosaic mode display of video  
Methods and systems for mosaic mode display of video are disclosed. Aspects of one method may include generating video data for a plurality of video windows using a single video feeder module...
8102401 Display controller operating mode using multiple data buffers  
A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of...
8063907 Apparatus and method for selectable hardware accelerators in a data driven architecture  
A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A...
8004523 Translation of register-combiner state into shader microcode  
An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state...
7978200 Raster-order pixel dithering  
Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for...
7928990 Graphics processing unit with unified vertex cache and shader register file  
Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared...
7864185 Register based queuing for texture requests  
A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture...
7852341 Method and system for patching instructions in a shader for a 3-D graphics pipeline  
A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D...
7847803 Method and apparatus for interleaved graphics processing  
The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a...
7821520 Fragment processor having dual mode register file  
A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader...
7812847 Method and apparatus for providing bandwidth priority  
A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel...
7788656 System for reducing the number of programs necessary to render an image  
Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to...
RE41523 Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets  
A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for...
7755634 System, method and computer program product for branching during programmable vertex processing  
A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a...

Matches 1 - 50 out of 254 1 2 3 4 5 6 >