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7636834 Method and apparatus for resetting a gray code counter  
Aspects of the invention may include gradually decrementing or incrementing a write pointer ( 370 ) associated with a data buffer such as the FIFO buffer ( 310 ) until a reset value of the write...
7570266 Multiple data buffers for processing graphics data  
Multiple output buffers are supported in a graphics processor. Each output buffer has a unique identifier and may include data represented in a variety of fixed and floating-point formats (8-bit,...
7570270 Buffer for driving display with asynchronous display engine  
Methods and systems for processing pixels within a decoded video stream are disclosed. Processed pixels may be received within the decoded video stream and may be buffered in a buffer at a first...
7565490 Out of order graphics L2 cache  
Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that...
7551176 Systems and methods for providing shared attribute evaluation circuits in a graphics processing unit  
Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics...
7546480 High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements  
In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow...
7487450 Computer display system, computer apparatus and display apparatus  
A personal computer ( 101 ) includes a control signal output unit ( 104 ) that outputs, to a display device ( 113 ), a control signal for switching between a TV format video signal and a computer...
7469356 Signals crossing multiple clock domains  
Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A number...
7425961 Display panel driver unit  
To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port...
7426594 Apparatus, system, and method for arbitrating between memory requests  
Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory...
7423652 Apparatus and method for digital video decoding  
The decoding method is disclosed. The steps of the method includes recording each status of a plurality of data blocks of compressed macroblocks indicated by a first pointer to a first pointer...
7400328 Complex-shaped video overlay using multi-bit row and column index registers  
A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that...
7349027 Scan converter  
The scan converter comprises first and second memories 3, 7 , a frame memory 5 ; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate...
7333116 Data processor having unified memory architecture using register to optimize memory access  
In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is...
7321369 Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device  
An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should...
RE39898 Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems  
A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an...
7287107 Method and apparatus for passive PCI throttling in a remote server management controller  
The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop...
7274371 Display controller and associated method  
A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory...
7259765 Head/data scheduling in 3D graphics  
A system for processing graphics data for a stream of graphics primitives, such as triangles. The system has a plurality of memories each for storing an index of the primitive. A controller selects...
7248265 System and method for processing graphics operations with graphics processing unit  
Disclosed is a system and method for processing graphic operations on a plurality of data structures of an image with a graphics processing unit and memory. The disclosed techniques of the system...
7243253 Repeating switching of a cross-connect and a timing source in a network element through the use of a phase adjuster  
A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an...
7215339 Method and apparatus for video underflow detection in a raster engine  
An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises apparatus for detecting one or more video...
7081896 Memory request timing randomizer  
Methods and apparatus for changing the timing of memory requests in a graphics system. Reading data from memory in a graphics system causes ground bounce and other electrical noise. The resulting...
7071944 Video and graphics system with parallel processing of graphics windows  
A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing...
7064764 Liquid crystal display control device  
A FIFO section having a FIFO memory is provided between a memory control section and a CPU_I/F section in a path through which image data outputted from a CPU is written into the video memory. Data...
7050063 3-D rendering texture caching scheme  
A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme...
7034840 Method for an image reducing processing circuit  
A method for an image reducing processing circuit includes the memory architecture of two FIFO units. The method includes the following steps of: providing an input processing unit receiving...
7006115 Supporting variable line length in digital display timing controllers using data enable signal  
A digital display unit which receives horizontal lines of unequal length in a V-active region and computes an average length of the lines. The average is used to generate horizontal line demarkers...
6999089 Overlay scan line processing  
An overlay video processing system provides an early start to pixel processing for the next overlay scan line. The overlay processor begins processing the next overlay scan line while still...
6999090 Data processing apparatus, data processing method, information storing medium, and computer program  
An information storing medium storing coded data of a content in segment units stores data including information of a horizontal video size, a vertical video size, a video depth, a maximum video...
6995770 Command list controller for controlling hardware based on an instruction received from a central processing unit  
A command list controller for controlling hardware based on an instruction received from a central processing unit (CPU) is provided. Specifically, the controller of the present invention retrieves...
6989837 System and method for processing memory with YCbCr 4:2:0 planar video data format  
A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged...
6975309 Display driver, and display unit and electronic instrument using the same  
A display driver capable of implementing natural moving image display with a reduced power consumption, based on display data of following frame is generated on a cycle longer than a read cycle for...
6956577 Embedded memory system and method including data error correction  
A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the...
6943800 Method and apparatus for updating state data  
In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a...
6937242 3-D graphics chip with embedded DRAM buffers  
A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes...
6917366 System and method for aligning multi-channel coded data over multiple clock periods  
A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or...
6897874 Method and apparatus for providing overlay images  
A circuit for providing an overlay in a window on a computer output display including scaling circuitry, storage circuitry for receiving a plurality of lines of source data, input circuitry for...
6870518 Controlling two monitors with transmission of display data using a fifo buffer  
A method for controlling two monitors on the basis of an input-side pixel data stream, in which one part of each line of the input-side pixel data stream is displayed on one of the monitors and...
6847369 Optimized packing of loose data in a graphics queue  
A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has...
6831653 Graphics pixel packing for improved fill rate performance  
A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize...
6812928 Performance texture mapping by combining requests for image data  
An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of...
6803916 Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization  
A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of...
6802036 High-speed first-in-first-out buffer  
A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first...
6791559 Parameter circular buffers  
A 3D graphics accelerator in which vertex data is locally cached, at individual rendering subsystems, in circular buffers which are NOT large enough to hold the maximum number of data fields for...
6784892 Fully associative texture cache having content addressable memory and method for use thereof  
A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The...
6775421 Method and apparatus of image processing while inputting image data  
An input image processing apparatus includes a FIFO memory (FIFO-S) in which region selection information for specifying a selected region in an input image frame, in order to consecutively store...
6766410 System and method for reordering fragment data based upon rasterization direction  
A system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the fragments are placed into a first and second data fragment buffer such that the data fragments are...
6756988 Display FIFO memory management system  
A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register...
6741257 Graphics engine command FIFO for programming multiple registers using a mapping index with register offsets  
A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for...
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