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6704023 3-D graphics chip with embedded DRAMbuffers  
A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes...
6690379 Computer system controller having internal memory and external memory control  
The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised...
6674423 Drive unit and liquid crystal device  
It is an object to provide a drive unit capable of properly responding to an access request from a microprocessor side and an access request from a display section side, and further of realizing a...
6670959 Method and apparatus for reducing inefficiencies in shared memory devices  
A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels'...
6654021 Multi-channel, demand-driven display controller  
A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between...
6614440 System and method for load balancing in a multi-channel graphics system  
A pull-model system and method provides display data over a network to a plurality of display devices having the same or different video format requirements. Utilization of image memory bandwidth...
6600492 Picture processing apparatus and picture processing method  
In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing...
6593931 Method and apparatus for improving system memory bandwidth utilization during graphics translational lookaside buffer cache miss fetch cycles  
An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first...
6563506 Method and apparatus for memory bandwith allocation and control in a video graphics system  
A method and apparatus for allocation and control of memory bandwidth within a video graphics system is accomplished by first determining the memory bandwidth needs of each of the plurality of...
6564304 Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching  
A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access...
6542159 Apparatus to control memory accesses in a video system and method thereof  
A method and apparatus for dynamic issuing of memory access instructions. In particular, a specific data access request that is about to be sent to a memory, such as a frame buffer, is dynamically...
6515672 Managing prefetching from a data buffer  
A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer...
6504549 Apparatus to arbitrate among clients requesting memory access in a video system and method thereof  
A method and apparatus dealing with optimizing the arbitration between clients requesting data. In particular, a set of rules determining which client request will provide an optimized subsequent...
6323866 Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system  
An integrated circuit device is adapted for use in a computer system that includes a processing unit, a host bus connected to the processing unit, an input/output bus, a peripheral device connected...
6091431 Method and apparatus for improving processor to graphics device local memory performance  
A graphics device implemented in accordance with one embodiment of the invention includes a first request path to a local memory interface for low-priority read transactions and a second request...
6078337 Maintaining consistency of cache memory data by arbitrating use of a connection route by plural nodes  
In a system in which a plurality of nodes are connected using a light wavelength multiplexing connection route which can simultaneously connect nodes using light beams of a plurality of different...
6078338 Accelerated graphics port programmable memory access arbiter  
A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that...
6057862 Computer system having a common display memory and main memory  
A memory architecture having one or more shared high-bandwidth memory subsystems each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem,...
6058459 Video/audio decompression/compression device including an arbiter and method for accessing a shared memory  
An electronic system provides direct access between a first device and a decoder/encoder and a memory. The electronic system can be included in a computer in which case the memory is a main memory....
6008823 Method and apparatus for enhancing access to a shared memory  
The present invention is directed to providing an organized memory which is accessed by multiple memory controllers while still exploiting the efficiencies which the organized memory was intended...
6002409 Arbitration for shared graphics processing resources  
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for...
5982360 Adaptive-selection method for memory access priority control in MPEG processor  
An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU, an audio decoder, a video decoder, an...
5959640 Display controllers  
An LCD panel controller includes a panel display driver driving a display panel having an inherent line input buffer, a memory/interface block, a frame memory and a host computer. The memory...
5953019 Image display controlling apparatus  
An image display control apparatus comprising: a plurality of image data storing units, provided corresponding to the plurality of the frames, for storing image data of frames respectively;...
5903283 Video memory controller with dynamic bus arbitration  
In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than...
5872577 Device for decoding signals of the MPEG-type  
The invention relates to a device for decoding encoded digital signals of the MPEG-type, comprising different modules (M1, M2, M3, . . . ), provided for communicating with an external random-access...
5861893 System and method for graphics data concurrency and coherency  
A graphics controller enhances concurrency among multiple pipelines, provides high throughput to graphics resources between 2D and 3D pipelines spawned by an application, and provides low latency...
5854638 Unified memory architecture with parallel access by host and video controller  
In a unified memory computer system architecture, the unified memory is divided into at least two banks of memory. All but one of the memory banks is reserved for access exclusively by the host...
5835101 Image information processing apparatus having means for uniting virtual space and real space  
An image information processing apparatus includes a cross bar switch circuit receiving first image information which indicates a two-dimensional image and second image information which indicates...
5818468 Decoding video signals at high speed using a memory buffer  
A method for decoding and displaying video signals using a memory buffer, in which a speed of a write operation for a memory buffer is adjusted to avoid overtaking a read operation for the same...
5809278 Circuit for controlling access to a common memory based on priority  
An access control apparatus comprises a memory accessed by a plurality of devices, a circuit for giving priority levels to the requests of these devices in access to the memory, a circuit for...
5793384 Image decoder with bus arbitration circuit  
An image decoder has a bus arbitrating circuit for controlling the use of the bus by any one of input bit stream buffer control circuit, decoding circuit, and image output control circuit. The bus...
5794072 Timing method and apparatus for interleaving PIO and DMA data transfers  
The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is...
5781927 Main memory arbitration with priority scheduling capability including multiple priorty signal connections  
A main memory arbitration arrangement for a computer system. It features the ability to set priorities between a main system and peripheral system to optimize system efficiency. The arbitration...
5774131 Sound generation and display control apparatus for personal digital assistant  
An improved sound generation and display control apparatus for a personal digital assistant capable of improving the system thereof and a transmission performance for various kinds of display...
5767866 Computer system with efficient DRAM access  
A computer system includes one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for providing a visible display to a user of the computer system. The...
5748203 Computer system architecture that incorporates display memory into system memory  
A computer architecture that incorporates display memory into system memory is disclosed, which comprises a memory, a memory controller and a display controller. Both of the memory controller and...
5740383 Dynamic arbitration priority  
An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the...
5706482 Memory access controller  
In order to write data flowing in continuously into an image memory consisting of a single port RAM without lack and to read data out of the image memory continuously without lack in parallel, a...
5699086 Method and apparatus for controlling image display  
A system for controlling an image display which enables the efficiency of transfer of image data to be greatly improved when a control processor and display control unit access an image memory at...
5682522 Shared memory architecture of graphics frame buffer and hard disk cache  
A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter,...
5678036 Graphics system and method for minimizing idle time of a controller of the graphics system  
A method for minimizing idle time of a controller in a graphics system, which includes a graphics memory and a graphics accelerating device that interconnects the controller and the graphics...
5673416 Memory request and control unit including a mechanism for issuing and removing requests for memory access  
The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various...
5657055 Method and apparatus for reading ahead display data into a display FIFO of a graphics controller  
A graphics controller that uses two MREQ priority levels (low and high) to retrieve display data from a frame buffer into a CRT FIFO. The graphics controller sends the high priority MREQ signal to...
5606428 Image compression systems with optimized data access  
An image compression system has an image memory accessible from the image bus. Compressed data are stored in a dual-ported memory accessible from both the image bus and the host bus. The...
5579473 Interface controller for frame buffer random access memory devices  
A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches...
5502808 Video graphics display system with adapter for display management based upon plural memory sources  
Video graphics display system having a display adapter connected between a host processor (2) and a display unit (6). The display adapter includes a video memory (4) which has first and second...
5486876 Video interface unit for mapping physical image data to logical tiles  
A video interface unit for transferring image data between video memory and video processing components interfaces with a video bus. The video interface unit has a partionable data buffer. The...
5461679 Method and apparatus for encoding/decoding image data  
An apparatus and method for processing video data for compression/decompression in real-time. The apparatus comprises a plurality of compute modules, in a preferred embodiment, for a total of four...
5450542 Bus interface with graphics and system paths for an integrated memory system  
A low-cost computer system which includes a single shared memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the...
Matches 51 - 100 out of 115 < 1 2 3 >