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7619631 |
Methods and systems for performing anti-aliasing operations with multiple graphics processing units
A technique for performing an anti-aliasing operation by multiple graphics processing units includes utilizing a first graphics processing unit to generate a first subset of filtered data resulting...
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7598959 |
Display controller
Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock...
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7589734 |
Data display system, data relay device, data relay method, data system, sink device, and data read method
A repeater comprises an EDID memory to store a control data and a memory control unit. The memory control unit is configured to make access to the EDID memory to read the control data therefrom,...
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7571296 |
Memory controller-adaptive 1T/2T timing control
Circuits, methods, and apparatus that adaptively control 1 T and 2 T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as...
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7562184 |
DRAM controller for graphics processing operable to enable/disable burst transfer
An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for...
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7536511 |
CPU mode-based cache allocation for image data
An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a...
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7532218 |
Method and apparatus for memory training concurrent with data transfer operations
Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first...
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7522171 |
On-the-fly reordering of 32-bit per component texture images in a multi-cycle data transfer
A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a...
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7518599 |
Display control device and method
A display control device and a display control method for use in a portable electronic apparatus are disclosed. The portable electronic apparatus includes a main controller and a display panel. The...
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7505301 |
Apparatus and method of driving memory for display device
A display driver having Dynamic Random Access Memory (DRAM) cells and a method of controlling the timing of the display driver are disclosed. The display driver includes memory cells each of which...
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7495668 |
Display controller with display memory circuit
A display memory circuit includes a drawing memory and a dynamic display memory. The drawing memory stores data and at least a portion of the data are possibly rewritten into a new data at a third...
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7490208 |
Architecture for compact multi-ported register file
Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port...
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7489316 |
Method for frame rate conversion
A method for converting a frame rate of a video signal comprising a data enable signal by means of a first buffer and a second buffer is disclosed. The method comprises: alternatively accessing the...
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7475210 |
Data stream generation method for enabling high-speed memory access
An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit...
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7474421 |
Printing apparatus and method of displaying explanations of printing apparatus
A printer specifies at least one arbitrary option out of a plurality of options displayed on a display screen as a tentative option, determines the tentative option as a determined option...
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7382366 |
Method, apparatus, system, and graphical user interface for selecting overclocking parameters of a graphics system
Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are...
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7349027 |
Scan converter
The scan converter comprises first and second memories 3, 7 , a frame memory 5 ; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate...
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7202882 |
Liquid crystal display device
A liquid crystal display device employing an overshooting driving method is provided which is capable of reducing memory capacity of a frame memory used to delay input data. The above liquid...
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7176928 |
Recovery of a serial bitstream clock at a receiver in serial-over-packet transport
A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a...
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7126608 |
Graphics processor and system with microcontroller for programmable sequencing of power up or power down operations
A graphics processor or display device including a microcontroller that functions as a sequencer, a computer system including at least one such graphics processor or display device, and a...
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7099989 |
System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an...
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7081896 |
Memory request timing randomizer
Methods and apparatus for changing the timing of memory requests in a graphics system. Reading data from memory in a graphics system causes ground bounce and other electrical noise. The resulting...
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7032092 |
Memory controller for supporting a plurality of different memory accesse modes
A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals...
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7030871 |
Active matrix display device
This invention is directed to the active matrix display device with an imaging speed rapid enough for the moving image display and the small power consumption. The selector makes the switch between...
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6977655 |
Dual mode DDR SDRAM/SGRAM
A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device,...
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6924807 |
Image processing apparatus and method
An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the...
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6919900 |
Methods and systems for preparing graphics for display on a computing device
Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying...
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6917365 |
Processor provided with a slow-down facility through programmed stall cycles
A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image...
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6912638 |
System-on-a-chip controller
A system-on-a-chip controller having a first processor and a second processor. The first processor provides control processing and image processing. The second processor provides image processing....
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6912000 |
Picture processing apparatus
A picture processing apparatus is composed of a plurality of picture processing systems. Each picture processing system includes an identical picture processing IC (integrated circuit) and a...
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6894692 |
System and method for sychronizing video data streams
A system for synchronizing video data streams utilizes a plurality of buffer pairs and buffering logic. The buffering logic is configured to receive image frames from a plurality of asynchronous...
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6833833 |
Feedback path for video benchmark testing
A feedback path to the processor for a video signal in a computer. The video image data is not normally subjected to benchmark testing because it would make it susceptible to illegal copying. The...
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6806883 |
System and method for handling display device requests for display data from a frame buffer
A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller...
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6778175 |
Method of arbitration of memory request for computer graphics system
The present invention, a method of the arbitration of memory request for a computer graphics system, consecutively services the requests having the same type in the same period, thereby increasing...
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6756988 |
Display FIFO memory management system
A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register...
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6750876 |
Programmable display controller
A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is...
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6747656 |
Image processing apparatus and method of the same, and display apparatus using the image processing apparatus
An image processing apparatus and method, and a display apparatus capable of preventing field tearing caused by memory overrun even when performing a read operation and a write operation of...
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6674423 |
Drive unit and liquid crystal device
It is an object to provide a drive unit capable of properly responding to an access request from a microprocessor side and an access request from a display section side, and further of realizing a...
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6664968 |
Display device and image displaying method of display device
The monitor system comprises the display device which has a screen having a display area virtually divided into a plurality of sub-screens. Provided are graphics adapters, each of which has two...
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6657634 |
Dynamic graphics and/or video memory power reducing circuit and method
An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory...
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6593939 |
Image display device and driver circuit therefor
An image display device includes a display panel having predetermined numbers of pixels defined in horizontal and vertical directions, respectively, and an interpolated-data generation circuit...
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6580432 |
Spread spectrum FIFO and method for storing data for multiple display types
A FIFO memory device, FIFO control method and graphics processing system are disclosed which incorporate spread-spectrum EMI compensation. In one embodiment, a FIFO memory device and method...
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6570572 |
Line delay generator using one-port RAM
A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the...
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6515672 |
Managing prefetching from a data buffer
A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer...
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6496192 |
Modular architecture for image transposition memory using synchronous DRAM
A memory architecture for a video transpose memory employs SDRAM memory devices which are arranged in memory rows such that elements in a single row may be accessed without memory set-up latency....
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6433785 |
Method and apparatus for improving processor to graphics device throughput
An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory...
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6392619 |
Data transfer device and liquid crystal display device
In a data transfer circuit, a hold signal generating circuit generates and outputs a hold signal Hold when transmission data is equal to transmission data one cycle before, and sets a 3-state...
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6340973 |
Memory control unit and memory control method and medium containing program for realizing the same
A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data...
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6192455 |
Apparatus and method for preventing access to SMRAM space through AGP addressing
A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and...
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6184905 |
Method and apparatus for processing video graphics information at different operating rates
A method and apparatus for processing video data at various optimum operating rates is accomplished by a video graphics circuit that includes a video graphics module, a buffer and a memory...
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