|
Match
|
Document |
Document Title |
|
|
7443251 |
Digital phase and frequency detector
Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use,...
|
|
|
7443247 |
Circuit arrangement for detection of a locking condition for a phase locked loop, and a method
A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is coupled to a charge pump. Furthermore, the...
|
|
|
7439817 |
Frequency tuning range extension and modulation resolution enhancement of a digitally controlled oscillator
A novel apparatus and method of extending the frequency tuning range and improving the modulation resolution of an RF digitally controlled oscillator (DCO). In addition to the coarse PVT MIM...
|
|
|
7439812 |
Auto-ranging phase-locked loop
A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit....
|
|
|
7439724 |
On-chip jitter measurement circuit
An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal...
|
|
|
7436265 |
Clock generator and clock generating method using delay locked loop
Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock...
|
|
|
7432769 |
Oscillator circuit
The oscillating unit 11 generates a signal having a frequency of n*f, i.e., n times a target frequency f. The control voltage generation circuit 21 compares the phase difference between a...
|
|
|
7429883 |
Oscillator configured to complete an output pulse after inactivation
An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving...
|
|
|
7425874 |
All-digital phase-locked loop for a digital pulse-width modulator
A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation...
|
|
|
7423492 |
Circuit to reset a phase locked loop after a loss of lock
A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into...
|
|
|
7424083 |
PLL noise smoothing using dual-modulus interleaving
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens”...
|
|
|
7420426 |
Frequency modulated output clock from a digital phase locked loop
A frequency modulated output of a digital locked loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The...
|
|
|
7417510 |
Direct digital interpolative synthesis
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N...
|
|
|
7408416 |
Phase locked loop, signal generating apparatus and synchronization method
A phase locked loop for outputting a high frequency signal by executing synchronization and frequency conversion based on an input signal includes a control-type oscillator, and a phase comparator...
|
|
|
7406297 |
Clock generation circuit and semiconductor device provided therewith
It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no...
|
|
|
7400205 |
Frequency synthesizer and oscillation control method of frequency synthesizer
The present invention provides a frequency synthesizer capable of switching an oscillation frequency band while maintaining a lock state realized with a small-scale and low-current-consumption...
|
|
|
7400204 |
Linear phase detector and charge pump
A phase detector detects a phase difference between a first and second signal received by a phase detector. A charge is supplied by a charge pump circuit that corresponds to the phase difference...
|
|
|
7394319 |
Pulse width modulation circuit and multiphase clock generation circuit
A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation...
|
|
|
7394418 |
Apparatus comprising a sigma-delta modulator and method of generating a quantized signal-delta modulator
A method of generating a quantized signal in a Sigma-Delta modulator ( 25 ) comprises the steps of feeding a modulator input signal to a quantizer ( 15 ) via at least one integrator ( 12, 13 );...
|
|
|
7394320 |
Phase-locked loop and method for operating a phase-locked-loop
A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a...
|
|
|
7385539 |
All-digital phase locked loop (ADPLL) system
An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop...
|
|
|
7385451 |
Arrangement, phase locked loop and method for noise shaping in a phase-locked loop
A noise shaping arrangement for a phase locked loop includes a first order sigma-delta modulator arranged to provide a first-order quantized output and a feedback path output. A second order...
|
|
|
7375592 |
System and method for maintaining an accurate frequency on a voltage controlled oscillator
A method for phase-locking a voltage controlled oscillator is disclosed. The method comprises receiving, at a phase detector, a phase input signal and a phase feedback signal from the voltage...
|
|
|
7375591 |
Robust false locking prevention in referenceless frequency acquisition
An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that...
|
|
|
7372340 |
Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages
A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a...
|
|
|
7369000 |
Adaptive frequency detector of phase locked loop
An adaptive frequency detector used in a phase locked loop for detecting a frequency difference between an input signal and an output clock generated from an oscillator of the phase locked loop...
|
|
|
7365607 |
Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL)
A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the...
|
|
|
7358820 |
Method and device for stabilizing a transfer function of a digital phase locked loop
In a method for stabilizing a transfer function of a digital phase locked loop a random digital signal is fed into the phase locked loop. The phase locked loop comprises the transfer function and a...
|
|
|
7352251 |
Systems and methods for suppressing feedback and reference noise in a phase lock loop circuit
Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an oscillation control source, and a sample and...
|
|
|
7352297 |
Method and apparatus for efficient implementation of digital filter with thermometer-code-like output
A technique is disclosed for processing a binary coded signal to generate a thermometer coded signal. Such technique includes the following steps. A binary coded input signal is obtained. A binary...
|
|
|
7345549 |
Phase locking on aliased frequencies
A phase-locked loop ( 200 ) includes a sampler ( 202 ), a phase detector ( 210 ), a loop filter ( 212 ), and a VCO ( 214 ). The loop achieves frequency multiplication without the need for a divider...
|
|
|
7342459 |
Clock reproduction circuit
A clock reproduction circuit receives a multi-valued input data signal to generate a reproduced clock signal with a higher accuracy. The clock reproduction circuit includes a data judgement block...
|
|
|
7327197 |
Radiation hardened phase locked loop
A method and apparatus for providing a radiation hardened Phase Locked Loop (PLL) are presented. The radiation hardened PLL includes an adjustable bandwidth loop filter. The adjustable filter...
|
|
|
7323940 |
Adaptive cycle-slipped detector for unlock detection in phase-locked loop applications
An adaptive cycle-slipped detector (“ACSD”) for use in a Phase-Locked Loop (“PLL”) circuit. The ACSD may include a phase comparator, a phase shifter in signal communication with the phase...
|
|
|
7323946 |
Lock detect circuit for a phase locked loop
An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a...
|
|
|
7321649 |
Phase locked loop with improved phase lock/unlock detection function
A phase locked loop (PLL) having an improved phase unlock detection function generates a clock pulse signal at a frequency from a synchronization signal of a cathode ray tube (CRT) monitor and...
|
|
|
7317359 |
Circuits and methods for phase locked loop lock window detection
Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference...
|
|
|
7315218 |
Method and apparatus to center the frequency of a voltage-controlled oscillator
A circuit and method are provided for calibrating an analog oscillator in the digital domain. The circuit and method disclosed herein centers an oscillation frequency of an analog oscillator by...
|
|
|
7312642 |
Continuous, wide-range frequency synthesis and phase tracking methods and apparatus
Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In...
|
|
|
7312668 |
High resolution PWM generator or digitally controlled oscillator
A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal...
|
|
|
7310021 |
Phase-locked loop with tunable-transfer function
Embodiments of a phase-locked loop having a tunable-transfer function are presented herein. In implementations, a multipulse generator coupled between the chase frequency detector and charge pump...
|
|
|
7304518 |
Track and hold circuit
A track and hold circuit ( 1 ) comprising:—a linear amplifier ( 2 ) receiving a differential analog signal (D+, D−) and being controlled by a first binary clock signal (H+) having a first...
|
|
|
7304545 |
High latency timing circuit
A phase locked loop (PLL) circuit, comprises a frequency integrator circuit that receives a target signal, a phase shift signal and a frequency gain correction parameter and that selectively...
|
|
|
7298216 |
Fine clock resolution digital phase locked loop apparatus
A digital phase locked loop apparatus includes an input signal time detecting device that detects a phase of an input signal with prescribed time resolution obtained by dividing a cycle of an...
|
|
|
7292110 |
Self-test digital phase-locked loop and method thereof
A phase-locked loop (PLL) apparatus utilizes a digital control unit to perform a stable phase-locking and self-testing. The PLL circuit internally generates a set of digital parameters. The set of...
|
|
|
7285999 |
Circuit for use in frequency or phase detector
A tracking data cell ( 10 ) comprising: —a pair of track and hold circuits ( 1, 1 ′) coupled to a first multiplexer ( 5 ), —a clock signal (H+, H−) being inputted substantially in...
|
|
|
7282999 |
Method and device for generating a clock signal using a phase difference signal and a feedback signal
A method and a device for generating a clock signal (F out ) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal...
|
|
|
7283001 |
Noise-shaping amplifier with waveform lock
A generalized amplifier architecture is described which employs noise-shaping feedback, and for which the output waveform closely resembles the input waveform.
|
|
|
7279987 |
Method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator
A method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator are disclosed. A model of a phase locked loop to be simulated in a digital simulator...
|
|
|
7279993 |
Phase-locked loop
A phase-locked loop includes an oscillator, a phase detector coupled to the oscillator, a charge pump coupled to the phase detector, a filter coupled to the charge pump, a voltage controlled...
|