Matches 101 - 150 out of 338 < 1 2 3 4 5 6 7 >
Match Document Document Title
6604233 Method for optimizing the integrated circuit chip size for efficient manufacturing  
The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and, for each offset, a number of...
6600345 Glitch free clock select switch  
A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output...
6600355 Clock generator circuit providing an output clock signal from phased input clock signals  
A clock generator circuit accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency...
6593780 Circuit for selectively generating an output signal from one or more clock signals  
The invention relates to a circuit ( 100 ) with which one of a plurality of input clock signals (CLK_SRC 1, . . . , CLK_SCR_n) can be selected and passed on to an output signal (CLK_OUT). The...
6590430 Dual use of an integrated circuit pin and the switching of signals at said pin  
In a signal processing system with an IC having an intrinsic signal provided at a pin of the IC, a first operational function (de-emphasis) for the signal is provided at the pin, and further along...
6583651 Neural network output sensing and decision circuit and method  
A device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device has a differential amplifier configuration having...
6577169 Clock selection circuit for eliminating short clock signal generated when switching clock signals produced by one clock generator to another clock generator  
The present invention relates to a clock selection circuit which can eliminate short clock signals when switching clock signals produced by one clock generator to clock signals produced by another...
6566912 Integrated XOR/multiplexer for high speed phase detection  
A high speed phase detector utilizes an integrated XOR/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/MUX circuit combines the functionality of an XOR...
6556000 Fast edge generator with wide dynamic range  
The electronic calibration equipment for verifying the high frequency characteristics of electronic test equipment, including oscilloscopes arid time interval analyzers is provided. An electronic...
6525591 Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit  
A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit...
6515533 Multi-input comparator  
A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator...
6512409 Signal switching circuit with reduced number of diodes used  
A signal switching circuit has first to fourth diode pairs each comprising two series-connected diodes disposed respectively between a first input terminal and a first output terminal, between a...
6509771 Enhanced operational frequency for a precise and programmable duty cycle generator  
A precise and programmable duty cycle adjuster which can produce a user definable duty cycle clock signal comprises a digital to analog converter (DAC), low pass filter (LPF), operational...
6507934 Apparatus and method for source synchronous link testing of an integrated circuit  
An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links...
6504891 Timer circuit with programmable decode circuitry  
A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the...
6501304 Glitch-less clock selector  
A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is...
6499133 Method of optimizing placement of elements  
An initial arrangement is effected based on a net list and a cell library. Combination functions are extracted from a cost function. An optimum estimated temperature is calculated based on the...
6486712 Programmable switch  
A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass...
6472909 Clock routing circuit with fast glitchless switching  
A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select...
6456147 Output interface circuit  
An output interface circuit realizes a fast and stable interface operation without any chip-size increase even if the external supply voltage varies within a specific range (e.g., from 5 V to 3.3 V...
6452425 Automatic frequency rate switch  
A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The...
6452426 Circuit for switching between multiple clocks  
A circuit to synchronously select one of the multiple clocks is presented. In one embodiment the selection circuit consists of four main blocks. These are the stable selects block, the decoder...
6453425 Method and apparatus for switching clocks presented to synchronous SRAMs  
A method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response to a...
6441668 Digital device with internal differential signal generator  
A device includes a first input pin, a second input pin, a differential signal generator, and a differential receiver. The first input pin is adapted to receive a first signal. The second input pin...
6429698 Clock multiplexer circuit with glitchless switching  
A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select...
6417717 Hierarchical multiplexer for analog array readout  
A unique hierarchical multiplexer is employed to multiplex signals read out from analog array elements one at a time to an output. In an embodiment of the invention, the multiplexer switching...
6417718 Semiconductor device without limitation on insert orientation on board  
An internal input voltage generating/external output voltage generating circuit is provided within a semiconductor device, a voltage on a pad corresponding to a supply pin terminal is detected to...
6411134 Spike-free clock switching  
A circuit for spike-free clock switching which offers asynchronous switching between two clock signals of the same frequency and of any desired phase angle, which is purely digital, which can be...
6411135 Clock signal switching circuit  
A clock signal switching circuit that switches between two clock signals having a phase difference. The clock signal switching circuit includes a first selector that selects one of the clock...
6400188 Test mode clock multiplication  
A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of...
6380775 Multiplexed distribution system for CMOS signals  
First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are...
6377108 Low jitter differential amplifier with negative hysteresis  
A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to...
6369637 Analog BiCMOS multiplexers with CMOS control signals  
High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low...
6369636 Method, architecture and circuit for selecting, calibrating and monitoring circuits  
A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal....
6342795 Control circuit having clock control unit  
Disclosed is a control circuit of a simplified circuit configuration and control while power consumed by the continuous supply of a clock signal to a functional block which is in an inoperative...
6329861 Clock generator circuit  
A clock generator circuit has a pulse generator with an output connected to a multiplexer and an output connected via a clocked latch to a second input of the multiplexer. The clock latch is...
6329862 Reference frequency signal switching circuit capable of adjusting level of external reference frequency signal and outputting resultant signal  
A reference frequency signal switching circuit of the invention comprises: a internal oscillator for generating an internal reference frequency signal; an external reference frequency signal input...
6323716 Signal distributing circuit and signal line connecting method  
A signal distributing circuit of the invention includes a first element which outputs a first signal and a second signal which is opposite to that of the first signal. The circuit is provided with...
6310509 Differential multiplexer with high bandwidth and reduced crosstalk  
A multiplexer includes a first input device that receives a first input signal and a first select signal. When the first select signal has a first state, the first input device generates a first...
6300816 Feedforward-controlled sense amplifier  
A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled...
6297684 Circuit and method for switching between digital signals that have different signal rates  
A circuit for switching digital signals on a plurality of signal lines where signals on different signals line may have different signal rates includes a controller that prevents a switch from...
6292038 Smooth clock switching for power managed PCI adapters  
The present invention includes a method and apparatus for smooth transitions (switching) between asynchronous clocks without the occurrence of glitches. In one embodiment the present invention is...
6271693 Multi-function switched-current magnitude sorter  
A signal sorter for magnitude sorting among a number of signals is disclosed that allows for magnitude sorting of a number of signals in an ascending or descending ordered manner governed by the...
6242961 Methods and circuits for restoration of a drooped DC signal  
Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of...
6239626 Glitch-free clock selector  
A pair of synchronized clock sources provides phase and frequency synchronous first and second clocks accompanied by first and second control signals to a clock selection circuit having a data...
6218887 Method of and apparatus for multiplexing multiple input signals  
A multiplexer selects multiple input signals to produce an output in which the distortion associated with switching is minimized. Selection of the multiple input signals is performed within a...
6211721 Multiplexer with short propagation delay and low power consumption  
A digital multiplexer with low power consumption and a data to output propagation delay of about one gate includes a plurality of pairs of emitter coupled input transistors. The emitters of each...
6198311 Expandable analog current sorter based on magnitude  
A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents to be sorted, a winner-take-all...
6185627 Analog and digital audio auto sense  
A method and apparatus for selectively sending a first signal or a second signal to an output signal are described. An electrical characteristic of a device coupled to the output is determined,...
6172537 Semiconductor device  
A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further...
Matches 101 - 150 out of 338 < 1 2 3 4 5 6 7 >