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7626524 |
Multi-channel sample and hold circuit and multi-channel A/D converter
A multi-channel sample and hold circuit includes an operational amplifier, plural electric charge setting channels. Each of the electric charge setting channels includes an input terminal, an...
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7612586 |
Low noise analog sampling circuit and a method for low noise sampling of an analog signal
A low noise analog sampling circuit that includes a transistor connected to a first feedback loop and to a second feedback loop. During a second operational phase the second feedback loop provides...
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7583166 |
Inductor Q factor enhancement apparatus has bias circuit that is coupled to negative resistance generator for providing bias signal
The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative...
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7564273 |
Low-voltage comparator-based switched-capacitor networks
Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The...
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7545296 |
Interleaved track and hold circuit
The invention relates to an interleaved track and hold circuit for tracking and holding a value of a continuous input signal and to provide discrete values thereof, wherein the circuit comprises a...
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7541846 |
Sample-and-hold apparatus and operating method thereof
A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling...
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7532042 |
Precision sampling circuit
A sampling circuit includes an input voltage source; a first switch having an input operatively connected to the input voltage source; a sampling capacitor operatively connected to an output of the...
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7504866 |
Output hold circuits for sample-data circuits
A sampled-data analog circuit uses zero-crossing detector. A waveform generator produces a plurality of segments of ramp at the output. An output of a zero crossing detector controls a sampling...
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7501863 |
Voltage margining with a low power, high speed, input offset cancelling equalizer
A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets...
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7495479 |
Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit
Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to...
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7486115 |
Sampled-data circuits using zero crossing detection
A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing...
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7479811 |
Sample/hold circuit module
A sample/hold circuit module. The sample/hold circuit module comprises a sample/hold circuit, an S/H controller, a pass transistor, and a high voltage generator. The sample/hold circuit comprises a...
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7477079 |
Single ended switched capacitor circuit
A single-ended, non-differential switched capacitor circuit is disclosed which removes the effect of common mode noise. To this end, the circuit creates a capacitance divider using the sampling...
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7477078 |
Variable phase bit sampling with minimized synchronization loss
Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling...
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7459943 |
High accuracy sample and hold circuit having a common negative input terminal
A high accuracy sample and hold circuit including a first switch, a second switch, a first capacitor, a second capacitor and an amplifier is disclosed. The first capacitor receives and saves a...
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7443209 |
PWM LED regulator with sample and hold
Improved stability in a regulator having a sample-and-hold. Coupling an input voltage to an input node of the sample-and-hold circuit is provided. Activating the sample-and hold circuit in response...
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7439777 |
Double feedback rotary traveling wave oscillator driven sampler circuits
A sampling circuit and method are disclosed. The sampling circuit includes a buffer, a holding capacitor, a set of switches, and at least two voltage references. The buffer drives buffered analog...
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7439778 |
Signal sampling apparatus and method
A signal sampling apparatus for generating an output signal according to an input signal is disclosed. The signal sampling system includes a sample and hold circuit and a gain controller. The...
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7427880 |
Sample/hold apparatus with small-sized capacitor and its driving method
A sample/hold apparatus includes first, second and third power supply terminals to which first, second and third power supply voltages are applied. The second power supply voltage is an...
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7423458 |
Multiple sampling sample and hold architectures
A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an...
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7397287 |
Sample hold circuit and multiplying D/A converter having the same
A sample hold circuit includes an op-amp, first capacitors provided on an inverting side of the op-amp and second capacitors provided on a non-inverting side. The sample hold circuit is configured...
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7394309 |
Balanced offset compensation circuit
Balanced offset compensation is provided for a differential amplifier circuit. Two sets of three switches are employed between respective inputs and outputs of the differential amplifier to shunt...
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7385427 |
Sample-and-hold circuits having reduced channel conductance variation and methods of operation thereof
An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first...
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7332940 |
Voltage hold circuit and clock synchronization circuit
A voltage hold circuit which holds an input signal voltage includes a voltage comparator unit configured to output a result of comparison between a voltage of an externally inputted control signal...
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7315200 |
Gain control for delta sigma analog-to-digital converter
Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an...
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7304518 |
Track and hold circuit
A track and hold circuit ( 1 ) comprising:—a linear amplifier ( 2 ) receiving a differential analog signal (D+, D−) and being controlled by a first binary clock signal (H+) having a first...
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7301382 |
Data latch circuit and electronic device
The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a...
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7292071 |
Method and circuit for sampling/holding a signal
A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device,...
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7285999 |
Circuit for use in frequency or phase detector
A tracking data cell ( 10 ) comprising: —a pair of track and hold circuits ( 1, 1 ′) coupled to a first multiplexer ( 5 ), —a clock signal (H+, H−) being inputted substantially in...
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7274222 |
Control method for an analogue switch
Method for controlling an analogue switch including a transistor to which a variable analogue input voltage Vin is applied on a first terminal between a source terminal and a drain terminal of the...
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7271625 |
Sample-and-hold device having input stages of amplifier coupled to capacitors
A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output...
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7248082 |
Sample-hold circuit
A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an...
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7236017 |
High speed sample-and-hold circuit
The use of a dynamic current bias technique to dynamically bias a voltage switch of a sample-and-hold circuit is disclosed. Dynamically biasing the voltage switch mitigates nonlinear distortion...
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7233166 |
Bus state keepers
Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of...
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7224213 |
Switched capacitor ripple-smoothing filter
A switched-capacitor ripple-smoothing filter includes a first pair of capacitors. The filter is configured such that either capacitor in the first pair may be reset and have a terminal coupled to a...
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7221191 |
Signal samplers with enhanced dynamic range
Signal sampler embodiments are provided for processing input signals along signal paths in response to mode-command signals. They include a follower transistor with a control terminal and a current...
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7218154 |
Track and hold circuit with operating point sensitive current mode based offset compensation
A track and hold (or sample and hold) offset compensated amplifier circuit that performs offset compensation in response to a comparison of sign (or sign and value) of the current forced to the...
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7215160 |
Switched operation amplifier
A switched operation amplifier including a biased circuit, an amplifier circuit, and a buffer circuit is provided. The biased circuit is to provide a first, a second, and a third biased signals by...
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7208983 |
Image-sensor signal processing circuit
By flexibly coping with both image sensors of a CCD sensor and a CMOS sensor without providing any external circuit, a signal processing is performed. In a sensor selecting switch provided in an...
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7194053 |
System and method for matching data and clock signal delays to improve setup and hold times
A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a...
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7187215 |
High dynamic range current-mode track-and-hold circuit
Embodiments of the current-mode track and hold circuit comprise a cascode input stage, a dynamic biasing stage, a cascode output stage, and a switch operable to interconnect the input stage and the...
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7167029 |
Sampling and level shifting circuit
A circuit comprising a first switch for sampling a differential signal and a second switch for level-shifting the sampled differential signal is disclosed. The first and second switches are...
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7157889 |
Sample and hold system for controlling a plurality of pulse-width-modulated switching power converters
A system is disclosed for controlling a plurality of pulse-width-modulated switching power converters. The system includes a sample and hold circuit which is configured to receive information at...
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7154306 |
Circuit and method for performing track and hold operations
A circuit and method for performing track and hold operations utilizes a circuit configuration in which a hold capacitor connected to a track signal path can be selectively isolated from an input...
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7142462 |
Input signal receiving device of semiconductor memory unit
A receiving device which may include a plurality of pre-amplifiers and a plurality of samplers. Each of the plurality of samplers is connected to the output ports of a corresponding pre-amplifier....
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7142030 |
Data latch circuit and electronic device
The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a...
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7119585 |
Sample and hold circuit based on an ultra linear switch
A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling...
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7113116 |
Sample and hold apparatus
An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then...
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7109902 |
Method and system for sampling a signal
According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal generated using a first clock signal by a...
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7106106 |
Clocked comparator circuit
A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has...
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