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7635992 Configurable tapered delay chain with multiple sizes of delay elements  
A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to...
7633326 Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof  
A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a...
7629825 Efficient delay elements  
Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of...
7626435 High resolution delay line architecture  
A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.
7619457 Programmable delay circuit  
A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both comprise transistors. With both the variable capacitor...
7605628 System for glitch-free delay updates of a standard cell-based programmable delay  
A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control...
7603095 Apparatus and method of switching intervals  
The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine...
7595673 Clock signal generator  
A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock...
7592842 Configurable delay chain with stacked inverter delay elements  
A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay...
7587541 Master-slave device communication circuit  
A master-slave device communication circuit includes a master device, a bus, and a slave device having a bus switch connected to the master device via the bus, and a status detecting circuit. The...
7586351 Apparatus and method for controlling delay of signal  
An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay...
7583124 Delaying stage selecting circuit and method thereof  
A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first...
7576585 Delay circuit  
A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit...
7573970 Prescaler and buffer  
A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive...
7571406 Clock tree adjustable buffer  
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of...
7570097 Electronic circuit with low noise delay circuit  
An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages ( 10 a - d ), coupled in a loop to form an oscillator for example. Each stage comprises an integrating...
7564285 Controllable delay line and regulation compensation circuit thereof  
A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output...
7548105 Method and apparatus for source synchronous testing  
A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be...
7545194 Programmable delay for clock phase error correction  
A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors...
7541851 Control of a variable delay line using line entry point to modify line power supply voltage  
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL....
7525356 Low-power, programmable multi-stage delay cell  
A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on...
7525364 Delay control circuit  
A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the...
7525363 Delay line and delay lock loop  
A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay...
7521977 Voltage-controlled oscillator generating output signal finely tunable in wide frequency range and variable delay circuits included therein  
A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input...
7518424 Slew rate controlled output circuit  
An output circuit comprises an input node, an output node, a first output transistor, a second output transistor, a first slew rate control circuit, and a second slew rate control circuit. The...
7515669 Dynamic input setup/hold time improvement architecture  
A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system...
7511547 Delay circuit, and testing apparatus  
A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal...
7504872 Generic flexible timer design  
One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks...
7495495 Digital I/O timing control  
When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals...
7466180 Clock network  
A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of...
7456671 Hierarchical scalable high resolution digital programmable delay circuit  
A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied...
7411434 Digitally programmable delay circuit with process point tracking  
A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the...
7403056 Delay apparatus and method thereof  
The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by...
7394302 Semiconductor circuit, operating method for the same, and delay time control system circuit  
A semiconductor circuit allows a timing adjustment after detailed routing without rearrangement and rerouting, an adjustment of delay variance due to process variation, and a delay adjustment even...
7394301 System and method for dynamically varying a clock signal  
According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to...
7391251 Pre-emphasis and de-emphasis emulation and wave shaping using a programmable delay without using a clock  
An adjustable-delay filter performs wave shaping to emulate pre-emphasis or de-emphasis of transmission-line signals. The adjustable-delay filter uses analog components and does not need a clock....
7386773 Method and system for testing distributed logic circuitry  
A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a...
7382170 Programmable delay circuit having reduced insertion delay  
A programmable delay circuit includes a plurality of delay blocks, a plurality of corresponding tri-state drivers and at least one decoder. The delay blocks are connected together so as to form a...
7378831 System and method for determining a delay time interval of components  
A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of...
7378892 Device for setting a clock delay  
A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are...
7375564 Time delay compensation circuit comprising delay cells having various unit time delays  
A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs...
7363401 Method and apparatus for controlling bus transactions depending on bus clock frequency  
A method and apparatus is presented that can provide first and second windows for driving data onto a bus in dependence on bus clock frequency. In one example, the speed of the bus clock is...
7362155 Method and apparatus for generating delays  
One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first...
7352223 Delay circuit having a capacitor and having reduced power supply voltage dependency  
A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor ( 106 ) charged with and discharging electric charge; a first switch ( 101 ) connected to...
7348821 Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors  
A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one...
7345520 Delay control in semiconductor device  
In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of...
7343507 Input circuit and method for the operation thereof  
An input circuit ( 1 ′) provided with a time delay element ( 40 ), which circuit is capable of being tested by a controlled high level or low level connection, and a method for the operation...
7339409 Slew rate controlled output driver for use in semiconductor device  
An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving...
7332950 DLL measure initialization circuit for high frequency operation  
A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry...
7330054 Leakage efficient anti-glitch filter  
A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter comprises a delay element and a coincidence detector...
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