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7622977 Ramped clock digital storage control  
Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to...
7571407 Semiconductor integrated circuit and method of testing delay thereof  
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
7557630 Sense amplifier-based flip-flop for reducing output delay time and method thereof  
A sense amplifier based flip flop and method thereof are provided. The example sense amplifier-based flip-flop may include a first current passing unit receiving a first clock signal with a first...
7548102 Data latch with minimal setup time and launch delay  
The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The...
7501871 Latch circuit  
A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D−). The latch further comprises a differential output with a non-inverting output (Q+)...
7489174 Dynamic flip-flop circuit  
A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level...
7486124 Current-controlled CMOS logic family  
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic...
7446581 Semiconductor integrated circuit with a logic circuit including a data holding circuit  
A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data...
7437800 Clock gating circuit  
Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a...
7405606 D flip-flop  
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and...
7323920 Soft-error rate improvement in a latch using low-pass filtering  
In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs...
7265589 Independent gate control logic circuitry  
A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an...
7265582 Level shifter  
A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a...
7259605 Pseudo true single phase clock latch with feedback mechanism  
A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage...
7242235 Dual data rate flip-flop  
A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the...
7236031 Fast bistable circuit protected against random events  
A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second...
7218162 Semiconductor integrated circuit having output circuit  
A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the...
7215940 Integrated circuit  
Embodiments of the present invention relates to an integrated mixer. A problem with producing low power consumption mixers is that they require a relatively high operating voltage due to the number...
7212056 Radiation hardened latch  
A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation...
7110718 Phase distortion using MOS nonlinear capacitance  
RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and...
7075350 Programmable low-power high-frequency divider  
A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the...
7068088 Soft-error rate improvement in a latch  
In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The...
6982583 Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process  
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic...
6972605 High speed semi-dynamic flip-flop circuit  
A high-speed semi-dynamic flip-flop circuit uses a keeper transistor to replace the back-to-back inverter keeper circuit of prior art semi-dynamic flip-flop circuits to avoid the fight between a...
6927614 High performance state saving circuit  
A state saving circuit includes a state saving latch powered by an un-interruptible power supply, and a cut-off control device powered by the un-interruptible power supply that selectively connects...
6882202 Multiple trip point fuse latch device and method  
A multiple trip point fuse latch device and method is disclosed. Multiple read inputs to a fuse latch enable the altering of the resistive trip point of the fuse latch. A multiple trip point fuse...
6864733 Data-enabled static flip-flop circuit with no extra forward-path delay penalty  
A logic circuit includes a data-enable controller for outputting a data value. When implemented as a master-slave flip-flop, a data enable signal controls the activation of a master stage of the...
6864732 Flip-flop circuit with reduced power consumption  
A low power flip-flop is disclosed. The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs. The flip-flop comprises...
6847808 Ultra-high linearity RF passive mixer  
A CMOS implemented passive mixer circuit for improving linearity performance in wireless communication systems is described, including dual pairs of NMOS FETs and dual pairs of PMOS FETs. Each NMOS...
6794916 Double edge-triggered flip-flops  
A static, double-edged triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a...
6794915 MOS latch with three stable operating points  
A tristable latch circuit fabricated utilizing standard MOS process technology includes a biasing element for identically biasing the MOS transistors in triode (as opposed to saturation) to...
6777992 Low-power CMOS flip-flop  
A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating...
6753707 Delay circuit and semiconductor device using the same  
A delay circuit includes an output circuit including first and second output elements. The first and second output elements are connected serially between a first power supply source and a second...
6731137 Programmable, staged, bus hold and weak pull-up for bi-directional I/O  
The present invention encompasses a bus hold and weak pull-up circuit. A resistor having a first node and a second node is coupled to a bi-directional I/O pin at the first node. The weak pull-up...
6720813 Dual edge-triggered flip-flop design with asynchronous programmable reset  
A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be...
6703881 Flip-flop circuit  
A low power, high performance flip-flop which does not require a full feedback path in the master stage includes a master stage driven by a data input, and an inverter. A slave stage includes a...
6696874 Single-event upset immune flip-flop circuit  
A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune...
6693476 Differential latch and applications thereof  
A differential latch includes a sample transistor section, a hold transistor section, a 1 st gating circuit and a 2 nd gating circuit. The sample transistor section is operably coupled to sample,...
6680638 High-speed discharge-suppressed D flip-flop  
A high-speed D flip-flop includes first and second precharge circuits, and first to fifth switching circuits. The first precharge circuit precharges first and second internal nodes to a first...
6621318 Low voltage latch with uniform sizing  
Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same...
6603964 Mixer with reduced carrier feedthrough  
A mixer circuit ( 100 ) includes two balanced transmission gate mixers ( 102, 104 ). The mixer circuit ( 100 ) balances charge injection mechanisms which reduces carrier feedthrough in the...
6563356 Flip-flop with transmission gate in master latch  
A method and apparatus for storing data in a master flip flop, comprising in combination receiving a clock signal having a first and second state, storing a master data state in a master storage...
6556060 Latch structures and systems with enhanced speed and reduced current drain  
Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are...
6545519 Level shifting, scannable latch, and method therefor  
Latch circuitry has a data input stage for sampling a first input signal responsive to a first timing signal and generating a signal on an intermediate node in the latch circuitry. The latch...
6525582 Latch operating with a low swing clock signal  
The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively...
6504412 Storage element with switched capacitor  
A latch includes a pair of inverters cross-coupled between a storage node and a feedback node. A capacitor is conditionally coupled to the feedback node through a pass gate such that the capacitor...
6483363 Storage element with stock node capacitive load  
A storage element includes a forward inverter and a feedback inverter cross-coupled between a storage node and a feedback node. A capacitive load within the feedback inverter is coupled to the...
6472919 Low voltage latch with uniform stack height  
Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by...
6462596 Reduced-transistor, double-edged-triggered, static flip flop  
A static, double-edge-triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a...
6433603 Pulse-based high speed flop circuit  
An integrated circuit device for synchronization of data in a data path includes a driver and a storage element coupled to the driver for driving the storage element. The storage element is coupled...
Matches 1 - 50 out of 149 1 2 3 >