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7626434 Low leakage state retention circuit  
In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage...
7623110 Systems for displaying images by utilizing horizontal shift register circuit for generating overlapped output signals  
Systems for displaying images are provided. An embodiment of such a system has a dynamic shift register. The dynamic shift register includes a first, second, third, fourth and fifth switching...
7622977 Ramped clock digital storage control  
Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to...
7612594 Latch circuit and semiconductor integrated circuit having the same  
A latch circuit includes first, second, and third inverter circuits, a switching element, and a capacitor element. The first inverter circuit and the second inverter circuit are cross-connected to...
7576582 Low-power clock gating circuit  
Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit...
7570080 Set dominant latch with soft error resiliency  
A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the...
7564290 Design structure for a high-speed level shifter  
Disclosed are embodiments of a design structure for a voltage level shifter circuit that operates without forward biasing junction diodes, regardless of the sequence in which different power...
7560965 Scannable flip-flop with non-volatile storage element and method  
A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for...
7548108 Semiconductor integrated circuit device with dual insulation system  
A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating...
7525362 Circuit for and method of preventing an error in a flip-flop  
A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with...
7525361 High speed flip-flops and complex gates using the same  
In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply...
7504871 Flip-flops and electronic digital circuits including the same  
A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active...
7501871 Latch circuit  
A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D−). The latch further comprises a differential output with a non-inverting output (Q+)...
7489174 Dynamic flip-flop circuit  
A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level...
7440534 Master-slave flip-flop, trigger flip-flop and counter  
A master latch ( 1 ) is formed from a static circuit, and a slave latch ( 2 ) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed...
7437800 Clock gating circuit  
Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a...
7420402 Flip-flops, shift registers, and active-matrix display devices  
A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output...
7405606 D flip-flop  
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and...
7405605 Storage elements using nanotube switching elements  
Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or...
7388420 Rewriteable electronic fuses  
Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values...
7388416 Latch circuit, 4-phase clock generator, and receiving circuit  
A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data...
7378890 Programmable low-power high-frequency divider  
Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency...
7345519 Flip-flop circuit  
A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that...
7324796 Low temperature co-fired ceramic sub-harmonic mixer  
A sub harmonic mixer has improved electrical performance in a small package size. The mixer has a low temperature co-fired ceramic substrate. Coupled lines are located within the substrate and...
7319353 Non-latching enveloping curves generator  
An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the...
7301382 Data latch circuit and electronic device  
The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a...
7301373 Asymmetric precharged flip flop  
A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During...
7292064 Minimizing timing skew among chip level outputs for registered output signals  
A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads...
7265589 Independent gate control logic circuitry  
A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an...
7265582 Level shifter  
A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a...
7262648 Two-latch clocked-LSSD flip-flop  
A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be...
7256634 Elastic pipeline latch with a safe mode  
An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an...
7256633 Systems for implementing high speed and high integration chips  
Disclosed are methods and systems for implementing various circuitry within a high speed, high frequency signal environment such as an integrated circuit. In one embodiment, an improved clock tree...
7248090 Multi-threshold MOS circuits  
A multi-threshold flip-flop includes a master latch, a slave latch, and at least one control switch. The master latch is composed of an input buffer formed with low threshold (LVT) transistors and...
7180351 Hybrid latch flip-flop  
A hybrid latch flip-flop is applied to an LCD. The hybrid latch flip-flop includes a negative pulse generation unit, a latch flip-flop, and a buffer unit. The latch flip-flop includes a sampling...
7170328 Scannable latch  
A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic...
7167033 Data retaining circuit  
A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are...
7164302 One gate delay output noise insensitive latch  
A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input...
7164301 State retention power gating latch circuit  
A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power...
7161404 Single event upset hardened latch  
A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the...
7142030 Data latch circuit and electronic device  
The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a...
7138842 Flip-flop circuit having low power data retention  
A flip-flop ( 10 ) comprises a first latch circuit ( 18 ), a second latch circuit ( 24 ), and a third latch circuit ( 26 ). The first latch circuit ( 18 ) is coupled to receive a clock signal and a...
7132871 Data retaining circuit  
A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are...
7129767 Methods of manufacture for a low control voltage switch  
A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to...
7126398 Method and an apparatus to generate static logic level output  
A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may...
7109776 Gating for dual edge-triggered clocking  
Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on...
7091766 Retention register for system-transparent state retention  
State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M 1 −M 3 ; M 1 −M 4 ) is used to load the shadow latch from...
7084683 High-speed differential flip-flop with common-mode stabilization  
A differential flip-flop ( 400 ) has an output stage ( 402 ) with first and second input terminals (X 1 , X 2 ), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a...
7084673 Output driver with pulse to static converter  
A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive...
7075350 Programmable low-power high-frequency divider  
A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the...
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