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7626433 Flip-flop circuit assembly  
A flip-flop circuit arrangement having a total of four differential amplifiers ( 1, 2, 3, 4 ), which are connected to one another to produce a D flip-flop, is specified. According to the suggested...
7612594 Latch circuit and semiconductor integrated circuit having the same  
A latch circuit includes first, second, and third inverter circuits, a switching element, and a capacitor element. The first inverter circuit and the second inverter circuit are cross-connected to...
7548103 Storage device having low power mode and methods thereof  
A storage device and methods thereof are disclosed. The device includes a clock control module and a latch. During normal operation, the clock control module provides a periodic clock signal to a...
7541841 Semiconductor integrated circuit  
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S 0 , a first node N 1 is L and a second node N 2...
7525371 Multi-threshold CMOS system and methods for controlling respective blocks  
A multi-threshold CMOS system and method controls a state of respective blocks individually. Each block includes a logic circuit having a logic transistor and a control transistor connected between...
7501871 Latch circuit  
A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D−). The latch further comprises a differential output with a non-inverting output (Q+)...
7489174 Dynamic flip-flop circuit  
A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level...
7427875 Flip-flop circuit  
Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and...
7405605 Storage elements using nanotube switching elements  
Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or...
7388416 Latch circuit, 4-phase clock generator, and receiving circuit  
A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data...
7345519 Flip-flop circuit  
A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that...
7332949 High speed pulse based flip-flop with a scan function and a data retention function  
Provided is a multi-threshold CMOS (MTCMOS) flip-flop for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal. The flip-flop...
7202703 Single stage level restore circuit with hold functionality  
A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry...
7176736 High-speed, current driven latch  
A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second...
7164293 Dynamic latch having integral logic function and method therefor  
A circuit ( 50 ) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase...
7102406 Phase detector, clock distribution circuit, and LSI  
A phase detector includes a first selection circuit configured to select a first clock from a first group of clocks supplied to the first selection circuit and to transmit the first clock, and at...
7095262 High reliability triple redundant latch with integrated testability  
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical...
7084673 Output driver with pulse to static converter  
A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive...
7064594 Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit  
Provided is a pass gate circuit capable of operating stably in a transition phase of an input signal, a self-refresh circuit including the pass gate circuit, and a method of controlling the pass...
7042263 Memory clock slowdown synthesis circuit  
Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and...
7002388 Nonvolatile flip-flop circuit and method of driving the same  
The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a...
6980789 Divider module for use in an oscillation synthesizer  
A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based...
6972605 High speed semi-dynamic flip-flop circuit  
A high-speed semi-dynamic flip-flop circuit uses a keeper transistor to replace the back-to-back inverter keeper circuit of prior art semi-dynamic flip-flop circuits to avoid the fight between a...
6940313 Dynamic bus repeater with improved noise tolerance  
In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while...
6937079 Single-transistor-clocked flip-flop  
The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the...
6911845 Pulse triggered static flip-flop having scan test  
A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test...
6891418 High speed flip-flop  
A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches...
6891398 Skewed falling logic device for rapidly propagating a falling edge of an output signal  
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the...
6842059 Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay  
A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of...
6822495 System and method for implementing a skew-tolerant true-single-phase-clocking flip-flop  
An exemplary skew-tolerant true-single-phase-clocking (TSPC) flip-flop is disclosed that reduces current spikes by allowing willful introduction of skew in the clock tree of a single-phase circuit...
6788122 Clock controlled power-down state  
A circuit and method reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method can be used for half-cycle latches and full cycle...
6741111 Data register for buffering double-data-rate DRAMs with reduced data-input-path power consumption  
A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops....
6714059 High-speed domino logic circuit  
An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed...
6703882 Dynamic circuits and static latches with low power dissipation  
A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET...
6693476 Differential latch and applications thereof  
A differential latch includes a sample transistor section, a hold transistor section, a 1 st gating circuit and a 2 nd gating circuit. The sample transistor section is operably coupled to sample,...
6667645 Pulsed clock signal transfer circuits with dynamic latching  
A signal transfer clocking circuit is disclosed which features a first stage including a first latch and a first, non-clocking circuit in series therewith and a second stage including a second,...
6636996 Method and apparatus for testing pipelined dynamic logic  
A method and apparatus for testing pipelined dynamic logic makes it possible to set and retrieve values from dynamic logic pipelines that have no internal latches. A modification to the pipeline...
6617899 Ultra high speed clocked analog latch  
An ultra high-speed clocked analog latch is revealed for use at clock speeds from 100 MHz to several GHz. The analog latch is used as a latching comparator for comparing a time-varying analog...
6573773 Conflict free radiation tolerant storage cell  
A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the...
6549060 Dynamic logic MUX  
A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the...
6535041 Strobe circuit keeper arrangement providing reduced power consumption  
A dynamic node keeper device for a dynamic strobe circuit is controlled by the signal at the intermediate node, that is, the signal at the output of the strobe component. By controlling the dynamic...
6525591 Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit  
A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit...
6512406 Backgate biased synchronizing latch  
An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias...
6486720 Flip-flop circuit arrangement with increased cut-off frequency  
In a flip-flop including a control element and a holding element, in which a first current causes the control element to set a logic state and a second current causes the holding element to...
6448831 True single-phase flip-flop  
Undersired glitches in output signals from TSPC- 1 flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock...
6448829 Low hold time statisized dynamic flip-flop  
A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase...
6424195 Dynamic flop with power down mode  
A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch...
6417710 Single event upset hardened latch circuit  
A single event upset (SEU) hardened latch circuit utilizing two cross-coupled inverters in which the voter output circuitry is fed back to the output node of the latch circuit.
6377096 Static to dynamic logic interface circuit  
A static logic signal to dynamic logic interface that produces a monotonic output. An inverse of a dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and...
6300809 Double-edge-triggered flip-flop providing two data transitions per clock cycle  
An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite...
Matches 1 - 50 out of 129 1 2 3 >