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8181073 SRAM macro test flop  
A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch...
8166286 Data pipeline with large tuning range of clock signals  
The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being...
8151152 Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method  
A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data...
8115530 Robust time borrowing pulse latches  
Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock...
8106698 Pulse-based flip-flop having scan input signal  
A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal...
8085076 Data retention flip flop for low power applications  
A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment...
8076964 Sampling circuit  
A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output...
8072251 Latch circuit and electronic device  
A latch circuit includes: four or more gates; three input terminals and one or two output terminals which are connected to at least one of the four or more gates; a feedback circuit in which...
8072252 Compound logic flip-flop having a plurality of input stages  
A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the...
8067971 Providing additional inputs to a latch circuit  
A latch circuit for retaining and transmitting an input data value is disclosed, along with a memory, and a method for retaining and transmitting data. The latch circuit includes a primary input...
8067970 Multi-write memory circuit with a data input and a clock input  
Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the...
8049546 Flip-flop, frequency divider and RF circuit having the same  
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first...
8024623 Misalignment compensation for proximity communication  
In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either...
8018271 Semiconductor integrated circuit  
A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in...
8013649 Dynamic clock feedback latch  
A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value...
7990180 Fast dynamic register  
A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of...
7979754 Voltage margin testing for proximity communication  
A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to...
7977983 Device having synchronizing capabilities  
A method and a device having synchronizing capabilities, the device includes; (i) a first circuit that is adapted to receive a first clock signal; (ii) a second circuit that is adapted to receive a...
7966589 Structure for dynamic latch state saving device and protocol  
The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a...
7965119 Device and method for handling metastable signals  
A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch...
7956661 Standard cell and semiconductor device  
The present invention provides a standard cell and a scan flip flop circuit capable of introducing a scan test also to a system LSI having an ACS circuit. One standard cell is configured by: a...
7924077 Signal processing apparatus including latch circuit  
A signal processing apparatus includes: a latch circuit; a set pulse generation circuit; a reset pulse generation circuit; and a correction set signal forming circuit. The correction set signal...
7904847 CMOS circuit leakage current calculator  
This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes...
7880502 Logic circuit  
A logic circuit with a simple configuration and good current efficiency is provided. The logic circuit includes a two-terminal bistable switching element (1) having characteristics which maintain...
7872513 Apparatus and circuit including latch circuit, and method of controlling latch circuit  
An apparatus includes a first selector which selects a test data during a first operation mode, and selects a first input data during a second operation mode, a first latch circuit which latches an...
7843243 Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit  
Example embodiments relate to an electronic circuit, for example, a flip-flop circuit, a pipeline circuit including the flip-flop circuit and a method for operating the flip-flop circuit. A...
7816966 Economy precision pulse generator  
A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a...
7795939 Method and system for setup/hold characterization in sequential cells  
An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing...
7782107 Method and apparatus for an event tolerant storage circuit  
An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event...
7768331 State-retentive master-slave flip flop to reduce standby leakage current  
A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip...
7768329 Semiconductor device  
A shift register capable of supplying only a necessary clock signal to a necessary unit register with simple constitution. A semiconductor device is provided with a shift register in which a...
7768294 Pulse latch circuit and semiconductor integrated circuit  
The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation...
7714627 Double-triggered logic circuit  
A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate...
7710177 Latch device having low-power data retention  
A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an...
7688125 Latched comparator and methods for using such  
Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch...
7671641 Frequency divider  
A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch...
7661047 Method and dual interlocked storage cell latch for implementing enhanced testability  
A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch...
7649394 Latch circuit  
A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a)...
7649396 Soft error rate hardened latch  
A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and...
7650454 Arbiter module providing low metastability failure probability  
An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving...
7626433 Flip-flop circuit assembly  
A flip-flop circuit arrangement having a total of four differential amplifiers (1, 2, 3, 4), which are connected to one another to produce a D flip-flop, is specified. According to the suggested...
7619455 Digital single event transient hardened register using adaptive hold  
By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data...
7609792 Multiple-input multiple-output multichip transceiver with correlated clock signals  
A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals...
7564072 Semiconductor device having junction termination extension  
A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is...
7521976 Low power high speed latch for a prescaler divider  
A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of...
7518426 Low power flip-flop circuit and operation  
A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received, and a...
7511894 Optical flip-flop circuit  
A flip-flop circuit of the present invention includes a first switch and a second switch which are connected in series to each other. The first switch includes: two input ports upon which light...
7508239 Pattern sequence and state transition triggers  
A pattern sequence and state transition trigger generator provides a trigger when a specified transition from one pattern/state to another pattern/state occurs in a set of input signals. Decoders...
7501871 Latch circuit  
A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D−). The latch further comprises a differential output with a non-inverting output (Q+) a...
7489174 Dynamic flip-flop circuit  
A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level...
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