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7622973 |
Pulse control device
Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively...
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7605626 |
Clock generator and clock duty cycle correction method
A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock...
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7595686 |
Digital controller for high-frequency switching power supplies
A voltage controller ( 150 ), the controller comprising: a voltage comparator ( 700 ) operative to provide a digital error signal ( 152 ); a compensator ( 300 ) operative to determine a digital...
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7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
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7583120 |
Power supply controller and method therefor
In one embodiment, an error amplifier of a power supply controller is configured to receive a current sense signal prior to the current sense signal undergoing amplification.
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7570094 |
Automatic duty cycle correction circuit with programmable duty cycle target
A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of...
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7554372 |
Digital dead-time controller for pulse width modulators
Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and...
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7545191 |
Method for dividing a high-frequency signal
A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle...
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7542533 |
Apparatus and method for calibrating the frequency of a clock and data recovery circuit
Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that...
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7506126 |
Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals,...
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7495491 |
Inverter based duty cycle correction apparatuses and systems
Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits...
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7495490 |
Digital amplifier and method thereof
An apparatus includes a first trigger, a second trigger, a pulse generator, and a control unit. The first trigger generates a first trigger signal and a first level signal; the second trigger...
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7489173 |
Signal adjustment for duty cycle control
Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated...
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7486122 |
Digitized method for generating pulse width modulation signals
A digitized method for generating pulse width modulation (PWM) signals is disclosed. In the digitized method, multiphase PWM signals are generated by altering the reference levels so that fully on...
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7477084 |
Multi-phase power supply controller and method therefor
In one embodiment, a power supply controller is configured to use a plurality of ramp signals to generate a plurality of PWM control signals.
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7456668 |
Pulse width modulation circuit and switching amplifier using the same
A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C 1 during the first period T 1 of the clock signal MCLK based on a current based...
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7436235 |
Digital clock modulator
A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected...
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7430140 |
Method and device for improved data valid window in response to temperature variation
A memory architecture and a method of operating the same can provide a substantially constant data valid window (DVW) irrespective of a temperature for the memory device. Generally, a memory device...
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7423466 |
Apparatus for enabling duty cycle locking at the rising/falling edge of the clock
An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating...
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7411435 |
Duty detection circuit
A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in...
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7397291 |
Clock jitter minimization in a continuous time sigma delta analog-to-digital converter
A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital...
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7397290 |
Method and relative circuit for generating a control voltage of a synchronous rectifier
A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing...
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7378889 |
Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit
A pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit is used in a power supply. The present invention comprises a hysteresis...
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7375563 |
Duty cycle correction using input clock and feedback clock of phase-locked-loop (PLL)
A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop...
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7372312 |
Pulse width modulation generating circuit
A pulse width modulation (PWM) generating circuit includes a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a capacitor, and a diode. The first resistor...
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7368966 |
Clock generator and clock duty cycle correction method
A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock...
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7352220 |
Measuring average of phase voltage of a frequency converter based on an idealized waveform
A method and arrangement for determining the effective time of a voltage pulse of phase voltage generated by a frequency converter provided with an intermediate voltage circuit, the voltage pulses...
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7317341 |
Duty correction device
A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a...
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7312668 |
High resolution PWM generator or digitally controlled oscillator
A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal...
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7301417 |
Pulse width modulation method and apparatus
Disclosed is a pulse width modulation method and apparatus capable of expressing as many values as possible in a pulse width modulation (PWM) period, while maintaining the center of pulse energy...
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7256632 |
Pulse width modulation (PWM) controlling module and method for adjusting a PWM signal thereof
A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a...
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7242233 |
Simplified method for limiting clock pulse width
The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes...
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7230466 |
Data strobe signal generating circuit and data strobe signal generating method
Provided is a data strobe signal generating circuit capable of guaranteeing a preamble time (tRPRE). The data strobe signal generating circuit includes: a strobe output driver for outputting a data...
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7148738 |
Systems, devices, and methods for providing control signals
Certain exemplary embodiments comprise a system, comprising: an electrical isolator adapted to couple a processor of a programmable logic controller to a user load; a transistor adapted to provide...
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7138841 |
Programmable phase shift and duty cycle correction circuit and method
A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and...
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7132856 |
Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors
A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are...
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7116916 |
Method and apparatus for compacting data in a communication network
A pulse width of a pulse having a nominal pulse width is modulated in accordance with a digital value to be communicated. The number of clock cycles that the modulated pulse width exceeds the...
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7102388 |
Interface device and information processing system
A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an...
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7091763 |
Clock generation
Clock generation techniques are disclosed to provide clock generation with duty cycle replication. The clock generation techniques may further compensate for clock insertion delays and minimize...
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7088162 |
Circuit generating constant narrow-pulse-width bipolarity monocycles
A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate...
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7071748 |
Charge pump clock for non-volatile memories
A charge pump clock for a memory device wherein pump clock signals are generated at an adaptive rate. The circuit of the present invention generates clock edges at a minimum of T D seconds apart...
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7019574 |
Circuit and method for correction of the duty cycle value of a digital data signal
According to the invention, a duty cycle correction device is disclosed. The duty cycle correction device corrects the duty cycle value of a data signal as a function of a digital control signal...
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7005898 |
Programmable divider with built-in programmable delay chain for high-speed/low power application
A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are...
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7002386 |
Self-limiting pulse width modulation regulator
A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input...
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6992515 |
Clock signal duty cycle adjust circuit
Systems and methods for independently adjusting a duty cycle of an input clock signal in an IC to compensate for uncertainties and distortions in the logic signals resulting from the logic signals...
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6985018 |
Programmable, multi-turn, pulse width modulation circuit for a non-contact angular position sensor
A multi-turn pulse width modulation (PWM) generator for generating a PWM output corresponding to multiple 360 degree turns. A counter receives a reference signal, and counts a number of cycles of...
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6928573 |
Communication clocking conversion techniques
A plurality of groups of first flip-flops (group 40 of flip-flops A 1 -An−1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals...
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6927642 |
Duty cycle correction method for frequency synthesis
A duty cycle correction method converts a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that...
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6919749 |
Apparatus and method for a digital delay locked loop
A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay...
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6882196 |
Duty cycle corrector
A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a...
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