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7636001 |
Digital DLL circuit
A digital DLL circuit includes: a first register configured to hold a first delay specifying value to specify a delay of a rising edge side of a signal; a second register configured to hold a...
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7633324 |
Data output strobe signal generating circuit and semiconductor memory apparatus having the same
A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A...
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7634677 |
Circuit and method for outputting aligned strobe signal and parallel data signal
An output circuit includes a detector receiving a parallel data signal, detecting a level change degree for the parallel data signal between a first time point and a second time point, and...
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7629827 |
Semiconductor integrated circuit
The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803 , wherein a clock is delayed by a variable delay circuit 805 and...
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7629816 |
Method and apparatus for pre-clocking
A method and apparatus for pre-clocking have been disclosed. In one case pre-clocking is used to effectively decrease the delay to output timing with respect to a clock. In another case...
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7627003 |
Automatic clock synchronization and distribution circuit for counter clock flow pipelined systems
A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a...
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7627066 |
Apparatus for data recovery in a synchronous chip-to-chip system
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling...
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7627790 |
Apparatus for jitter testing an IC
An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a...
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7622971 |
Delay locked loop circuits and methods of generating clock signals
A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control...
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7620133 |
Method and apparatus for a digital-to-phase converter
A DPC ( 300 ) includes: a frequency source ( 310 ) for generating a clock signal; a delay line ( 320 ) for receiving the clock signal and generating phase-shifted clock signals at output taps; a...
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7620857 |
Controllable delay device
Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit...
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7619456 |
Wide frequency multi-phase signal generator with variable duty ratio and method thereof
A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential...
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7619454 |
Clock generator for semiconductor memory apparatus
The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay...
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7616030 |
Semiconductor device and operation method thereof
Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first...
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7612622 |
Method and device for determining a duty cycle offset
Embodiments of the present invention relate to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle. Embodiment...
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7605629 |
Adjusting circuit and method for delay circuit
Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals,...
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7605624 |
Delay locked loop (DLL) circuit for generating clock signal for memory device
A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock...
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7605623 |
Semiconductor memory apparatus with a delay locked loop circuit
A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to...
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7605625 |
Device, system and method of delay calibration
System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by...
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7602257 |
Signal generating circuit
A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive...
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7602224 |
Semiconductor device having delay locked loop and method for driving the same
A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a...
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7602223 |
Delay-locked loop circuit and method of generating multiplied clock therefrom
A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling...
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7599245 |
Output controller capable of generating only necessary control signals based on an activated selection signal
An output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe (CAS) latency,...
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7583124 |
Delaying stage selecting circuit and method thereof
A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first...
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7583118 |
Delay locked loop circuit
A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to...
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7576580 |
Energy efficient clock deskew systems and methods
Systems and methods for active clock deskew are provided. The disclosed systems/methods advantageously achieve desirable clock deskew at reduced power levels by employing a resistance-based...
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7576579 |
DLL circuit and semiconductor device including the same
A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK 1 , a second delay adjusting circuit that adjusts an amount of delay of a...
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7570097 |
Electronic circuit with low noise delay circuit
An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages ( 10 a - d ), coupled in a loop to form an oscillator for example. Each stage comprises an integrating...
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7560963 |
Delay-locked loop apparatus and delay-locked method
A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a...
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7557627 |
Semiconductor memory device for generating a delay locked clock in early stage
A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data...
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7558692 |
Consumption current balance circuit, compensation current amount adjusting method, timing generator, and semiconductor testing apparatus
A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay...
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7557628 |
Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay...
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7557561 |
Electronic device, circuit and test apparatus
There is provided an electronic device for receiving an input data signal and an input clock signal that indicates a timing to obtain the input data signal. The electronic device includes a first...
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7554371 |
Delay locked loop
A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the...
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7535275 |
High-performance memory interface circuit architecture
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially...
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7535274 |
Delay control circuit
A delay control circuit includes a first delay unit, a signal regulation unit, a selector and a second delay unit. The first delay unit is used for delaying an input signal and generates a delayed...
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7532051 |
Method and apparatus for selection of an internal or external time delay
A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time...
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7532050 |
Delay locked loop circuit and method
A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic....
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7525356 |
Low-power, programmable multi-stage delay cell
A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on...
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7525364 |
Delay control circuit
A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the...
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7525363 |
Delay line and delay lock loop
A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay...
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7525354 |
Local coarse delay units
Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a...
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7522686 |
CMOS burst mode clock data recovery circuit using frequency tracking method
Provided is a burst mode clock data recovery circuit for extracting clock information and data information from transmitted data to process data synchronized with clock. The circuit includes a...
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7519087 |
Frequency multiply circuit using SMD, with arbitrary multiplication factor
Disclosed is a frequency multiply circuit for outputting an output signal obtained by variably multiplying the frequency of an input signal includes a synchronous delay circuit, a multiplexing...
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7514974 |
Method and apparatus for adjusting on-chip delay with power supply control
An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator...
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7515003 |
Filter-based lock-in circuits for PLL and fast system startup
All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower...
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7511544 |
Digital DLL circuit for an interface circuit in a semiconductor memory
A digital DLL circuit includes: a first register configured to hold a delay specifying value to specify a delay; a second register configured to specify a correction value for a gate delay inside...
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7508245 |
Lock detector and delay-locked loop having the same
A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an...
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7501869 |
Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication
A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of...
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7495489 |
Frequency multiplying delay-locked loop
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the...
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