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7616037 |
Method and apparatus for controlling power-down mode of delay locked loop
A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit...
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7616036 |
Programmable strobe and clock generator
Timing test circuits, including programmable strobe and clock generators, may include at least two DLLs having differing numbers of delay elements thereby producing many timing signals having...
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7613254 |
Phase detector for comparing phases of data and a plurality of clocks
A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the...
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7612591 |
DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus
A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency...
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7610163 |
Method of controlling quality for a print controller
A method performed by a quality assurance integrated circuit for a print controller, the quality assurance integrated circuit comprising a memory; a system clock for generating a clock signal;...
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7609100 |
On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip
An on-chip signal waveform measurement apparatus mounted on an IC chip measures signal waveforms at detection points on the IC chip. A reference voltage generator successively generates reference...
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7605625 |
Device, system and method of delay calibration
System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by...
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7605624 |
Delay locked loop (DLL) circuit for generating clock signal for memory device
A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock...
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7605623 |
Semiconductor memory apparatus with a delay locked loop circuit
A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to...
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7605622 |
Delay locked loop circuit
A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller...
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7603095 |
Apparatus and method of switching intervals
The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine...
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7602224 |
Semiconductor device having delay locked loop and method for driving the same
A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a...
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7602223 |
Delay-locked loop circuit and method of generating multiplied clock therefrom
A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling...
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7598783 |
DLL circuit and method of controlling the same
A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction...
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7595673 |
Clock signal generator
A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock...
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7595672 |
Adjustable digital lock detector
An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a...
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7592846 |
Method for using digital PLL in a voltage regulator
A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from...
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7583119 |
Delay locked loop having small jitter and jitter reducing method thereof
A delay locked loop includes an auxiliary phase shifter for controlling a phase blending point after the delay locked loop is initially locked, thereby reducing jitter. A control circuit directs a...
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7583118 |
Delay locked loop circuit
A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to...
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7583117 |
Delay lock clock synthesizer and method thereof
A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase...
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7583115 |
Delay line off-state control with power reduction
A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference...
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7583103 |
Configurable time borrowing flip-flops
Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a...
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7581120 |
System and method for providing multi-point calibration of an adaptive voltage scaling system
A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point...
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7579889 |
Delay lock loop and phase angle generator
The provided delay lock loop delaying an input signal includes a quadrature generator, a voltage controller and a delay cell. The input signal is inputted into the quadrature generator and the...
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7576579 |
DLL circuit and semiconductor device including the same
A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK 1 , a second delay adjusting circuit that adjusts an amount of delay of a...
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7576576 |
Switchable PLL circuit
An electronic circuit includes a first and a second PLL stage (PLL 1 , PLL 2 ) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input...
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7573312 |
Apparatus and method of controlling operation frequency in DLL circuit
A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the...
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7573311 |
Programmable high-resolution phase delay
A programmable delay lock loop system provides a delayed output signal having a programmed delay from an input signal. A phase detector provides a phase delay signal indicative of an actual phase...
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7573308 |
Delay locked loop circuit for preventing malfunction caused by change of power supply voltage
A Delay Locked Loop (DLL) circuit prevents a malfunction caused by a change of a power supply voltage, and includes a first and a second delay lines and a first and a second signal processors for...
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7571406 |
Clock tree adjustable buffer
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of...
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7570093 |
Delay-locked loop and a delay-locked loop detector
A delay-locked loop detector detects a control voltage of a delay-locked loop, in which the delay-locked loop generates an output clock signal according to a delay time that is controlled by the...
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7567103 |
Apparatus for detecting and preventing a lock failure in a delay-locked loop
An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal...
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7567102 |
Delay locked loop circuit in semiconductor device and its control method
A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on...
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7567100 |
Input clock detection circuit for powering down a PLL-based system
An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic...
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7564283 |
Automatic tap delay calibration for precise digital phase shift
An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to...
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7560963 |
Delay-locked loop apparatus and delay-locked method
A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a...
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7560962 |
Generating an output signal with a frequency that is a non-integer fraction of an input signal
Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one...
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7557628 |
Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay...
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7557627 |
Semiconductor memory device for generating a delay locked clock in early stage
A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data...
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7557626 |
Systems and methods of reducing power consumption of digital integrated circuits
There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system...
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7555073 |
Automatic frequency control loop circuit
Provided is a frequency control loop circuit changing division ratios of a frequency synthesizer to oscillate frequencies in a broadband with high precision. The circuit comprises a clock...
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7554371 |
Delay locked loop
A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the...
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7551012 |
Phase shifting in DLL/PLL
The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A...
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7548105 |
Method and apparatus for source synchronous testing
A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be...
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7545193 |
Voltage-controlled delay circuit using second-order phase interpolation
Phase interpolation techniques for voltage-controlled delay line (VCDL) implementation are provided. The techniques of the invention may employ a second-order phase interpolation topology to...
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7545189 |
Delayed locked loop circuit
A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs...
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7541851 |
Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL....
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7536617 |
Programmable in-situ delay fault test clock generator
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in...
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7535275 |
High-performance memory interface circuit architecture
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially...
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7535274 |
Delay control circuit
A delay control circuit includes a first delay unit, a signal regulation unit, a selector and a second delay unit. The first delay unit is used for delaying an input signal and generates a delayed...
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