|
Match
|
Document |
Document Title |
|
|
7119592 |
Delay locked loop circuit with time delay quantifier and control
A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a...
|
|
|
7119523 |
Semiconductor chip
A semiconductor chip able to reduce wasteful power loss due to a margin of power supply voltage considering variation of characteristics. A voltage setting signal for setting the power supply...
|
|
|
7119589 |
Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof
A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to...
|
|
|
7119596 |
Wide-range programmable delay line
An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an...
|
|
|
7119593 |
Delayed signal generation circuits and methods
Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to...
|
|
|
7116147 |
Circuit and method for interpolative delay
A circuit and a method for interpolative delay is provided. The circuit includes a delay locked loop with interpolation delay. The delay locked loop includes a differential inverter, an...
|
|
|
7116142 |
Apparatus and method for accurately tuning the speed of an integrated circuit
An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in...
|
|
|
7116146 |
Digital DLL device, digital DLL control method, and digital DLL control program
A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T...
|
|
|
7116143 |
Synchronous clock generator including duty cycle correction
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input...
|
|
|
7116148 |
Variable delay line using two blender delays
A variable delay line comprises a first blender delay configured to provide a first signal, a second blender delay configured to provide a second signal complementary to the first signal, and a...
|
|
|
7113024 |
Circuit module with high-frequency input/output interfaces
The invention relates to a circuit module with high-frequency input/output interfaces, and in particular to a circuit realized on a chip, principally a monolithic integrated circuit having a...
|
|
|
7113015 |
Circuit for setting a signal propagation time for a signal on a signal line and method for ascertaining timing parameters
A tuning circuit for setting a signal propagation time on a signal line in an integrated circuit, particularly a DRAM circuit, has a transistor and a capacitor. A control connection of the...
|
|
|
7113011 |
Low power PLL for PWM switching digital control power supply
A timing source for a pulse generator is disclosed, which timing source includes an input for receiving a reference clock output at a reference operating frequency. An edge generator is provided...
|
|
|
7113012 |
Skew delay compensator
A skew delay compensator is provided including at least two communication interfaces, at least two conductors connected to the communication interfaces, adjustable delay lines connected to the...
|
|
|
7109766 |
Adjustable frequency delay-locked loop
A delay-locked loop 300 that includes: an adjustable frequency source ( 320 ) for generating a clock signal ( 322 ) having an adjustable frequency; an adjustment and tap selection controller (...
|
|
|
7109767 |
Generating different delay ratios for a strobe delay
A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to...
|
|
|
7109774 |
Delay locked loop (DLL) circuit and method for locking clock delay by using the same
A delay line unit of a delay locked loop (DLL) circuit, includes a first delay line having a plurality of first unit delays, each first unit delay having a first delay; a second delay line having a...
|
|
|
7111185 |
Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit
A method and apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second...
|
|
|
7106114 |
Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero
A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises...
|
|
|
7107475 |
Digital delay locked loop with extended phase capture range
A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the...
|
|
|
7102403 |
Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof
A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the output clock for generating...
|
|
|
7103492 |
Process independent delay chain
An integrated circuit has a circuit for adjusting the time period of an output signal. The adjustment can compensate for semiconductor processing variations varying from wafer to wafer. The circuit...
|
|
|
7102402 |
Circuit to manage and lower clock inaccuracies of integrated circuits
A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither,...
|
|
|
7103133 |
Register controlled delay locked loop circuit
A register controlled delay locked loop (DLL) includes a clock divider, a shift controller, a delay unit and a delay model to synchronize an external clock signal with an internal clock. The...
|
|
|
7098714 |
Centralizing the lock point of a synchronous circuit
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is...
|
|
|
7099232 |
Delay locked loop device
An apparatus for detecting locking information of a DLL clock in a semiconductor memory device includes a delayed locked loop for generating a first comparison signal and a first delay end signal;...
|
|
|
7098711 |
Semiconductor device, receiver circuit, and frequency multiplier circuit
A delay circuit is provided including: 2 n (n is a natural number) unit delay circuits for delaying an input clock signal (with the period of T) in accordance with a delay setting signal and...
|
|
|
7098710 |
Multi-speed delay-locked loop
A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a...
|
|
|
7100066 |
Clock distribution device and method in compact PCI based multi-processing system
Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon...
|
|
|
7095261 |
Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a...
|
|
|
7091760 |
DLL with adjustable phase shift using processed control signal
Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that...
|
|
|
7089440 |
Skew compensation for a multi-agent shared bus
A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the...
|
|
|
7088275 |
Variable clock rate analog-to-digital converter
An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing...
|
|
|
7088156 |
Delay-locked loop having a pre-shift phase detector
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted...
|
|
|
7088159 |
Register controlled delay locked loop and its control method
A register controlled delay locked loop (DLL), including: a coarse delay line for generating a delayed input clock signal by delaying an external clock signal; a fine delay line unit for receiving...
|
|
|
7088158 |
Digital multi-phase clock generator
A digital multi-phase clock generator includes a reference clock input and first and second digitally-programmable delay lines. The first and second delay lines are coupled in parallel with one...
|
|
|
7084682 |
Delay-locked loop circuit and method thereof for generating a clock signal
A delay-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled delay line and a coarse lock detector. The phase frequency detector generates an...
|
|
|
7081784 |
Data output circuit of memory device
A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable...
|
|
|
7081782 |
Locked loop with dual rail regulation
An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals,...
|
|
|
7078949 |
Analog delay locked loop having duty cycle correction circuit
An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase...
|
|
|
7079616 |
Process for generating a variable frequency signal, for instance for spreading the spectrum of a clock signal, and device therefor
The use of a PLL including a phase detector responsive to the phase difference between an input signal and a feedback signal and which pilots an oscillator in function of this difference, is...
|
|
|
7076013 |
Clock synchronization device
A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low...
|
|
|
7071746 |
Variable delay circuit
A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay...
|
|
|
7072433 |
Delay locked loop fine tune
A digital delay locked loop (DLL) includes a coarse delay segment and fine delay segment. The coarse delay segment includes a coarse delay range. The fine delay segment includes a fine delay range....
|
|
|
7071745 |
Voltage-controlled analog delay locked loop
An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage...
|
|
|
7068085 |
Method and apparatus for characterizing a delay locked loop
A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and...
|
|
|
7068084 |
Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device
In a delay locked loop (DLL) of a semiconductor memory device capable of compensating for delay of an internal clock signal by variation of driving strength of an output driver, a replica output...
|
|
|
7068202 |
Architecture for an algorithmic analog-to-digital converter
An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing...
|
|
|
7064592 |
Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device
A method of setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module is disclosed. The method includes determining whether a delay tap value needs to be adjusted based...
|
|
|
7061224 |
Test circuit for delay lock loops
A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the...
|