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Match Document Document Title
7330060 Method and apparatus for sigma-delta delay control in a delay-locked-loop  
Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated...
7330059 In-loop duty corrector delay-locked loop for multiphase clock generation  
A delay-locked loop (DLL) employs an in-loop duty cycle corrector (DCC) to provide accurate multiphase clock generation with 50% duty cycle. Each delay cell can advantageously provide both delay...
7328115 Quality assurance IC having clock trimmer  
A quality assurance integrated circuit for a print controller is provided. The IC has a memory, a system clock having a ring oscillator for generating a clock signal, clock trim circuitry for...
7327173 Delay-locked loop having a pre-shift phase detector  
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted...
7327174 Fast locking mechanism for delay lock loops and phase lock loops  
A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock...
7323918 Mutual-interpolating delay-locked loop for high-frequency multiphase clock generation  
A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an...
7323917 Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal  
An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control...
7323915 Delay locked loop with selectable delay  
A DLL includes a control module coupled with a phase detect signal. The phase detect signal is used by a control module to generate feedback and output select signals. The feedback and output...
7321248 Phase adjustment method and circuit for DLL-based serial data link transceivers  
A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer...
7319351 Delay generator with symmetric signal paths  
A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more...
7319354 Signal processing apparatus having internal clock signal source  
A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal...
7319345 Wide-range multi-phase clock generator  
A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a...
7317775 Switched deskew on arbitrary data  
A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and...
7312667 Statically controlled clock source generator for VCDL clock phase trimming  
The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations...
7308372 Phase jitter measurement circuit  
A method, an apparatus, and a system for phase jitter measurement circuits are described herein.
7304515 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process  
The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay apparatus with variably controllable...
7304516 Method and apparatus for digital phase generation for high frequency clock applications  
An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by...
7301378 Circuit and method for determining optimal power and frequency metrics of an integrated circuit  
One use for delay adjustment circuit ( 32 ), coarse-grain delay offset circuit ( 34 ), and fine-grain delay synthesis circuit ( 36 ) may be as part of a delay replication circuit ( 30 ) used to...
7301379 Systems and method for a delay locked loop with false-lock detection  
A DLL comprises detection circuitry configured to detect a too_slow and a too_fast operating state and correction circuitry configured to correct operation of the DLL when a too_fast or too_slow...
7298190 Phase locked loop having enhanced locking characteristics  
A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to...
7298191 Reset-free delay-locked loop  
A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock...
7298189 Delay locked loop circuit  
The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and...
7298192 Digital DLL device, digital DLL control method, and digital DLL control program  
A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T...
7295053 Delay-locked loop circuits  
A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase...
7292080 Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals  
Embodiments of the present invention generally provide improved techniques and circuit configurations for a delay-locked loop (DLL) circuit. In one embodiment, a first phase difference between an...
7292079 DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner  
A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals...
7289572 Method and system for scalable pre-driver to driver interface  
A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed. The system includes a predriver to driver interface...
7287200 Jitter applying circuit and test apparatus  
There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an...
7285996 Delay-locked loop  
A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output...
7287235 Method of simplifying a circuit for equivalence checking  
A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a...
7282973 Enhanced DLL phase output scheme  
A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted...
7282971 Digital delay lock loop  
A digital delay locked loop architecture is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit which monitors the frequency of the input clock...
7282974 Delay locked loop  
A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the...
7280930 Sequential timebase  
A method and apparatus for correcting for deterministic jitter in a sequential sampling timebase. The value of a fine analog delay is held at a substantially constant nominal rate during a duration...
7280419 Latency counter having frequency detector and latency counting method thereof  
The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one...
7279946 Clock controller with integrated DLL and DCC  
A clock controller for use with an off-chip driver and including a first delay element, a second delay element, a restore circuit, and an adjustment circuit. The clock controller includes a node...
7276946 Measure-controlled delay circuits with reduced phase error  
Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample...
7276947 Delay circuit with reset-based forward path static delay  
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the...
7276951 Delay line circuit  
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay...
7276944 Clock generation circuit and clock generation method  
A clock generation circuit and a clock generation method are provided, which are spread spectrum clock generation and accurate phase control of a reference clock signal and an output clock signal....
7276950 Prevention of the propagation of jitters in a clock delay circuit  
The clock delay circuit according to the present invention includes a delay circuit section, a selection circuit section, and jitter suppression elements. The delay circuit section provides a...
7274230 System and method for clockless data recovery  
A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating...
7274238 Digital circuit having delay circuit for adjustment of clock signal timing  
A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the...
7274236 Variable delay line with multiple hierarchy  
Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal,...
7274231 Low jitter frequency synthesizer  
A frequency synthesizer IC is disclosed that includes a variable delay circuit, a fractional-N phase locked loop circuit, and a feedback loop. The variable delay circuit is electrically coupled to...
7274239 Method and apparatus to set a tuning range for an analog delay  
An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector compares a reference signal and feedback...
7271634 Delay-locked loop having a plurality of lock modes  
A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to...
7271669 Voltage controlled oscillator and phase locked loop circuit having the same  
A voltage controlled oscillator and a phase locked loop circuit having the same reduce power consumption by using charges leaked into a ground voltage terminal for an output driving operation with...
7268599 Method and apparatus for buffer with programmable skew  
A method and apparatus for a buffer with programmable skew have been disclosed. Several output signals are generated. Based on one of the output signals several feedback signals are generated. The...
7268602 Method and apparatus for accommodating delay variations among multiple signals  
A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines...
Matches 201 - 250 out of 951 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >