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7492200 |
Delayed locked loop (DLL)
A delayed locked loop (DLL) circuit is provided which reliably provides an initial delay period of a delay line.
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7492199 |
Fully synchronous DLL with architected update window
The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least...
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7489170 |
Delay locked loop in synchronous semiconductor memory device and driving method thereof
A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating...
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7490273 |
Auto-calibration method for delay circuit
An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. If the number of accumulative errors of a designated delay chain as a current delay path is...
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7489171 |
Adaptive delay-locked loops and methods of generating clock signals using the same
A delay-locked loop (DLL) includes a delay line and a control circuit. The delay line delays an input clock signal based on at least one phase control signal to generate an output clock signal. The...
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7489168 |
Clock synchronization apparatus
According to an embodiment of the present invention, a clock synchronization apparatus includes a delay-correcting circuit which is supplied with an initial voltage, compares a phase of an external...
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7489169 |
Self-timed fine tuning control
A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the fine delay block is self tuning. The...
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7489587 |
Semiconductor memory device capable of controlling clock cycle time for reduced power consumption
Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the...
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7486319 |
Signal generating circuit including delay-locked loop and semiconductor device including signal generating circuit
According to a signal generating circuit including a delay-locked loop, a driving device including the signal generating circuit, and an image capturing apparatus including the signal generating...
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7486119 |
Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device
A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a...
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7486120 |
Delay ratio adjusting circuit, delayed pulse generation circuit, and pulse width modulation pulse signal generation device
Object To provide a highly accurate and stable pulse width modulation (PWM) pulse signal generation device compatible with high resolution images without increasing a basic frequency of an external...
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7487481 |
Receiver circuit for on chip timing adjustment
A structure for for maintaining signal integrity between integrated circuits residing on a printed circuit board. The structure has adjustable delay circuitry within the circuits and the adjustable...
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7482848 |
Internal clock generation circuits with improved locking speed and corresponding methods
Internal clock generation circuits are provided that include a first delay circuit that is responsive to a first clock signal, a coarse locking circuit that includes at least one analog synchronous...
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7482849 |
Clock signal synchronizing device, and clock signal synchronizing method
The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device ( 101 ) to be used with the synchronization of clock signals (CLK, DQS), comprising:
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7482850 |
Delay locked loop circuit and semiconductor integrated circuit device
A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control...
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7479816 |
Generating multiple delayed signals of different phases from a reference signal using delay locked loop (DLL)
A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay elements and a duty cycle correction...
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7477714 |
Phase adjusting circuit for minimized irregularities at phase steps
An integrated phase adjusting circuit ( 12 ) for the generation of a clock output signal (CLK out ) with a phase intermediate the phases of first and second input signals of equal frequency with a...
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7477715 |
Delay-locked loop circuit of a semiconductor device and method of controlling the same
A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby...
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7477083 |
DLL circuit feeding back ZQ calibration result, and semiconductor device incorporating the same
A delay amount variable circuit ( 8 ) adapted to change a delay amount according to a ZQ calibration result is inserted in a path of a DQ replica system. The delay amount of the path of the DQ...
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7474136 |
Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device
A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not...
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7471128 |
Delay signal generator and recording pulse generator
A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A...
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7471130 |
Graduated delay line for increased clock skew correction circuit operating range
Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement,...
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7471131 |
Delay locked loop with common counter and method thereof
A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain...
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7472304 |
Double data rate system
An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock...
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7471129 |
Device for utilization with the synchronization of clock signals, and clock signal synchronizing method
A clock signal synchronization method and an apparatus device for utilization with the synchronization of clock signals is disclosed. In one embodiment the apparatus includes a delay device with a...
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7459949 |
Phase detector circuit and method therefor
The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal,...
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7457392 |
Delay locked loop
A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals...
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7456666 |
Frequency-doubling delay locked loop
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay...
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7456664 |
Delay locked loop with precision controlled delay
The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second...
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7456665 |
Phase shifter
A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at...
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7453296 |
Delay locked loop having charge pump gain independent of operating frequency
A delay locked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A method for providing a constant gain for a charge pump component of a delay locked loop...
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7453297 |
Method of and circuit for deskewing clock signals in an integrated circuit
The methods and circuits of the various embodiments of the present invention relate to deskewing a generated clock signal. According to one embodiment, a method of deskewing a clock signal in a...
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7450675 |
Multi-channel receiver, digital edge tuning circuit and method thereof
A multi-channel receiver, digital edge tuning circuit and a method for operating the same is disclosed. The digital edge tuning circuit for tuning phases of an input signal and a clock signal,...
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7449930 |
Delay locked loop circuit
A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply...
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7447289 |
Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by...
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7446579 |
Semiconductor memory device having delay locked loop
A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an...
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7447106 |
Delay stage-interweaved analog DLL/PLL
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on...
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7443216 |
Trimmable delay locked loop circuitry with improved initialization characteristics
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by...
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7436231 |
Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase...
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7436228 |
Variable-bandwidth loop filter methods and apparatus
Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor...
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7436265 |
Clock generator and clock generating method using delay locked loop
Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock...
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7436230 |
Delay locked loop with improved jitter and clock delay compensating method thereof
A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component...
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7430680 |
System and method to align clock signals
A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer...
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7428284 |
Phase detector and method providing rapid locking of delay-lock loops
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between...
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7428286 |
Duty cycle correction apparatus and method for use in a semiconductor memory device
The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of...
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7425858 |
Delay line periodically operable in a closed loop
A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal,...
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7423466 |
Apparatus for enabling duty cycle locking at the rising/falling edge of the clock
An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating...
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7424634 |
System and method for reducing jitter of signals coupled through adjacent signal lines
A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects each of the transitions of the...
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7423464 |
Phase and amplitude modulator
The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to...
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7421048 |
System and method for multimedia delivery in a wireless environment
A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a...
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