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7576576 |
Switchable PLL circuit
An electronic circuit includes a first and a second PLL stage (PLL 1 , PLL 2 ) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input...
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7576579 |
DLL circuit and semiconductor device including the same
A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK 1 , a second delay adjusting circuit that adjusts an amount of delay of a...
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7573311 |
Programmable high-resolution phase delay
A programmable delay lock loop system provides a delayed output signal having a programmed delay from an input signal. A phase detector provides a phase delay signal indicative of an actual phase...
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7573308 |
Delay locked loop circuit for preventing malfunction caused by change of power supply voltage
A Delay Locked Loop (DLL) circuit prevents a malfunction caused by a change of a power supply voltage, and includes a first and a second delay lines and a first and a second signal processors for...
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7573312 |
Apparatus and method of controlling operation frequency in DLL circuit
A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the...
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7570093 |
Delay-locked loop and a delay-locked loop detector
A delay-locked loop detector detects a control voltage of a delay-locked loop, in which the delay-locked loop generates an output clock signal according to a delay time that is controlled by the...
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7571406 |
Clock tree adjustable buffer
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of...
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7567103 |
Apparatus for detecting and preventing a lock failure in a delay-locked loop
An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal...
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7567102 |
Delay locked loop circuit in semiconductor device and its control method
A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on...
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7567100 |
Input clock detection circuit for powering down a PLL-based system
An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic...
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7564283 |
Automatic tap delay calibration for precise digital phase shift
An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to...
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7560962 |
Generating an output signal with a frequency that is a non-integer fraction of an input signal
Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one...
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7560963 |
Delay-locked loop apparatus and delay-locked method
A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a...
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7557627 |
Semiconductor memory device for generating a delay locked clock in early stage
A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data...
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7557628 |
Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay...
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7557626 |
Systems and methods of reducing power consumption of digital integrated circuits
There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system...
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7554371 |
Delay locked loop
A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the...
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7555073 |
Automatic frequency control loop circuit
Provided is a frequency control loop circuit changing division ratios of a frequency synthesizer to oscillate frequencies in a broadband with high precision. The circuit comprises a clock...
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7551012 |
Phase shifting in DLL/PLL
The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A...
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7548105 |
Method and apparatus for source synchronous testing
A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be...
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7545189 |
Delayed locked loop circuit
A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs...
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7545193 |
Voltage-controlled delay circuit using second-order phase interpolation
Phase interpolation techniques for voltage-controlled delay line (VCDL) implementation are provided. The techniques of the invention may employ a second-order phase interpolation topology to...
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7541851 |
Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL....
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7535275 |
High-performance memory interface circuit architecture
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially...
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7535274 |
Delay control circuit
A delay control circuit includes a first delay unit, a signal regulation unit, a selector and a second delay unit. The first delay unit is used for delaying an input signal and generates a delayed...
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7536617 |
Programmable in-situ delay fault test clock generator
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in...
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7535273 |
Phase-locked loop circuit, delay locked loop circuit, timing generator, semiconductor test instrument, and semiconductor integrated circuit
A PLL and DLL are designed such that the power consumption can be reduced, the size can be easily reduced, the band of the locked loop can be a higher one, and the reliability can be improved....
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7532078 |
Scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics
A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as...
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7532050 |
Delay locked loop circuit and method
A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic....
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7528639 |
DLL circuit and method of controlling the same
A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external...
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7528638 |
Clock signal distribution with reduced parasitic loading effects
Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL)...
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7525363 |
Delay line and delay lock loop
A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay...
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7526056 |
Delay locked loop with low jitter
Digital delay locked loops which generate fixed angle delayed (e.g., quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature...
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7525355 |
Digital delay locked loop
A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the...
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7525354 |
Local coarse delay units
Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed signal, a second delayed signal, and a...
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7522686 |
CMOS burst mode clock data recovery circuit using frequency tracking method
Provided is a burst mode clock data recovery circuit for extracting clock information and data information from transmitted data to process data synchronized with clock. The circuit includes a...
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7518422 |
Switched capacitor for a tunable delay circuit
A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift...
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7514973 |
Circuit having a clock signal synchronizing device with capability to filter clock-jitter
A circuit having a clock signal synchronizing device with capability to filter clock-jitters is disclosed. One embodiment provides a delayed locked loop with capability to filter clock-jitter....
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7511544 |
Digital DLL circuit for an interface circuit in a semiconductor memory
A digital DLL circuit includes: a first register configured to hold a delay specifying value to specify a delay; a second register configured to specify a correction value for a gate delay inside...
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7511543 |
Automatic static phase error and jitter compensation in PLL circuits
An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to...
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7508245 |
Lock detector and delay-locked loop having the same
A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an...
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7501865 |
Methods and systems for a digital frequency locked loop for multi-frequency clocking of a multi-core processor
A method and systems for a digital frequency locked loop in a multi-core processor are provided. The method includes applying a dither modulation signal at a dither modulation frequency to modulate...
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7501869 |
Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication
A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of...
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7501868 |
Power supply voltage control apparatus
A power supply voltage control apparatus capable of freely setting a clock period setting margin according to a system clock frequency, and capable of converging power supply voltage to minimum...
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7496168 |
Phase-locked loop using multi-phase feedback signals
A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the...
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7495487 |
Delay-locked loop (DLL) system for determining forward clock path delay
A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages....
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7495489 |
Frequency multiplying delay-locked loop
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the...
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7495518 |
Automatic radio frequency feedback calibration circuit
A calibration circuit is configured to provide automatic feedback calibration during a tuning cycle. Automating the calibration process reduces the engineering evaluation time and mass production...
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7492850 |
Phase locked loop apparatus with adjustable phase shift
The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and...
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7492849 |
Single-VCO CDR for TMDS data at gigabit rate
A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking...
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