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6359483 Integrated circuit clock distribution system  
An improved clock distribution system is provided for a multi block network having a series of independent blocks, with each independent block having an average load tap signal. The clock...
6356158 Phase-locked loop employing programmable tapped-delay-line oscillator  
A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop...
6351169 Internal clock signal generating circuit permitting rapid phase lock  
An internal clock signal generating circuit according to the present invention has a minute delay stage that can change a delay amount minutely and a delay stage that changes its delay amount by a...
6351191 Differential delay cell with common delay control and power supply  
A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that...
6351167 Integrated circuit with a phase locked loop  
A phase regulator is connected, on the input side, to the output of a phase comparator and generates a control signal in a manner dependent on the phase difference ascertained by said comparator....
6351166 Semiconductor device with stable and appropriate data output timing  
A semiconductor device includes a timing-stabilization circuit which adjusts a phase of the synchronization clock signal. The semiconductor device further includes a control circuit which suspends...
6348823 Digital controlled oscillating circuit of digital phase lock loops  
A digital controlled oscillator (DCO) of a digital phase lock loop (PLL) is disclosed, wherein a fractional DCO structure is employed to provide the required target clock for comparing with the...
6349070 Packaged integrated circuit synchronous memory device with circuits for compensating clock signals having different loads using phase adjustments  
A phase difference between clock signals in an integrated circuit is determined after the integrated circuit is packaged. The phase difference can thereby be adjusted so that the effect of the...
6346839 Low power consumption integrated circuit delay locked loop and method for controlling the same  
A low power consumption delay locked loop for integrated circuit devices wherein a wider frequency range of operation is achieved by matching the delay of the clock comparison function of the phase...
6346838 Internal offset-canceled phase locked loop-based deskew buffer  
A phase lock loop-based deskew buffer circuit includes a fixed delay element to delay a feedback signal and to generate a first signal from the feedback signal. A delay locked loop (DLL) generates...
6342801 Duty cycle correction circuit of delay locked loop  
A duty cycle correction circuit of a delay locked loop circuit in a Rambus DRAM, decreasing a clock locking time by previously correcting a storage capacitor value to a setting value so as to...
6337590 Digital delay locked loop  
An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is...
6330197 System for linearizing a programmable delay circuit  
A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay...
6326812 Programmable logic device with logic signal delay compensated clock network  
An integrated circuit programmable logic device comprising: a plurality of programmable logic elements that are responsive to clock signals; a clock signal generation circuit which produces a first...
6323714 System and method for deskewing synchronous clocks in a very large scale integrated circuit  
A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and...
6323705 Double cycle lock approach in delay lock loop circuit  
A double data rate (DDR) synchronous dynamic RAM (SDRAM) includes delay lock loop circuitry which is designed so as to significantly reduce the locking period associated with achieving the lock...
6320436 Clock skew removal apparatus  
Digital clock deskew apparatus for synchronising the phase of a first and a second clock signal. The deskew apparatus includes a tapped delay line, selector apparatus and a phase detector.
6316976 Method and apparatus for improving the performance of digital delay locked loop circuits  
A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL...
6313675 Delay locked loop driver  
The present invention provides an improved, efficient DLL design. In one embodiment, it includes a voltage controlled delay line, a phase comparator, and a dynamic bias source. The delay line has...
6313676 Synchronous type semiconductor integrated circuit having a delay monitor controlled by a delay control signal obtained in a delay measuring mode  
A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a...
6314149 Method and apparatus for rephasing a voltage controlled clock, or the like  
A pulse rephasing circuit and method for receiving an input signal and generating an output signal includes a circuit for generating a control voltage of magnitude related to a phase difference...
6313679 Timing circuit  
A timing circuit which is used to synchronize different circuit to each other. The timing circuit includes adjustable delay apparatus which delay an input signal with a predetermined value. The...
6310928 PLL circuit  
A PLL circuit comprises a storage/control circuit for storing, in an associated manner, a plurality of PLL output frequencies to be designated, lock ranges including the PLL output frequencies in...
6310498 Digital phase selection circuitry and method for reducing jitter  
In systems embodying the invention a voltage responsive circuit is used to generate a number of different clock signals having the same frequency, with each clock signal being delayed relative to...
6304116 Delay locked looped circuits and methods of operation thereof  
The present invention provides delay locked loop circuits, phase detectors and methods for producing a delayed signal from a periodic input signal. An intermediate delay signal as well as an input...
6294938 System with DLL  
A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a...
6295328 Frequency multiplier using delayed lock loop (DLL)  
A frequency multiplier is provided that increases operational stability by using a Delay Locked Loop (DLL). The frequency multiplier includes a phase detector for detecting a phase difference...
6294937 Method and apparatus for self correcting parallel I/O circuitry  
3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That...
6292040 Internal clock signal generating circuit having function of generating internal clock signals which are multiplication of an external clock signal  
An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency divider, a phase comparator and a shift register. The selector alternately selects an external clock...
6285225 Delay locked loop circuits and methods of operation thereof  
A delay locked loop circuit includes a variable delay circuit that receives an input clock signal and produces a delayed clock signal that is variably delayed with respect to the input clock signal...
6281759 Digital frequency generation method and apparatus  
A method and a circuit are described for generating a frequency signal having fine frequency control, and which are suitable for implementation on an-integrated circuit. The output frequency is...
6281728 Delay locked loop circuit  
A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal; first oscillation means for generating a first pulse signal;...
6282253 Post-filtered recirculating delay-locked loop and method for producing a clock signal  
An apparatus for producing a clock signal includes a recirculating delay-locked loop operable to receive a reference clock signal, produce an output clock signal, and adjust the relative phase,...
6275079 Analog delay locked loop circuit  
An analog delay locked loop circuit includes: a phase detector detecting a phase difference between an external clock signal and an internal clock signal, a charge pump performing a pumping...
6275555 Digital delay locked loop for adaptive de-skew clock generation  
An apparatus including a phase detector to detect a phase difference between an output clock signal and a local reference clock signal comprising a first sampling circuit and a second sampling...
6272439 Programmable delay path circuit and operating point frequency detection apparatus  
A circuit for programmably generating a delay in a frequency monitor. In one embodiment, the circuit includes a delay cell. A delay cell controller is coupled to the delay cell. The delay cell...
6271697 Semiconductor integrated circuit device  
In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are...
6265947 Power conserving phase-locked loop and method  
A power conserving phase-locked loop achieves power savings by adding a switch which selectively enables the bias current for the charge pump associated with the phase comparator of the...
6265916 Clock multiplier circuit capable of generating a high frequency clock signal from a low frequency input clock signal  
A clock multiplier circuit comprises: a counter for counting the number of pulses of a predetermined output clock signal; an expected value generating circuit for generating an expected value for...
6262608 Delay locked loop with immunity to missing clock edges  
A method for determining whether to trigger a reset of a delay locked loop ("DLL") comprising calculating the difference in time between a reference clock and a delay clock; comparing the...
6262634 Phase-locked loop with built-in self-test of phase margin and loop gain  
A phase-locked loop (PLL) is provided, which includes a PLL reference input, a PLL output and a phase detection loop coupled between the PLL reference input and the PLL output. The phase detection...
6259290 Delay locked loop having a mis-lock detecting circuit  
A delay locked loop has a voltage-controlled delay section and a mis-lock detecting circuit. The voltage-controlled delay sections comprises a plurality of controlled delay circuits, including a...
6259293 Delay circuitry, clock generating circuitry, and phase synchronization circuitry  
Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a...
6259288 Semiconductor integrated circuit having a DLL circuit and a special power supply circuit for the DLL circuit  
A semiconductor integrated circuit has a DLL circuit for receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase...
6255880 One-shot DLL circuit and method  
A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the...
6252465 Data phase locked loop circuit  
A phase comparator circuit reducing the effects of offset and jitter, and a data Phase Locked Loop circuit incorporating the phase comparator circuit. The phase comparator circuit includes a Delay...
6252443 Delay element using a delay locked loop  
A delay locked loop circuit, in accordance with the invention, includes a delay line for providing a delay through the delay line in accordance with a control signal, the delay line being connected...
6242955 Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal  
A method and system for synchronizing a reference signal and an output signal produced by an electrical circuit, the electrical circuit comprising an analog portion and a digital portion, is...
6242954 Timing clock generation circuit using hierarchical DLL circuit  
The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase adjustment by smaller, fine delay unit....
6239634 Apparatus and method for ensuring the correct start-up and locking of a delay locked loop  
A delay locked loop (DLL) is described comprising: a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal, said specified amount controlled...
Matches 701 - 750 out of 948 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >