Matches 651 - 700 out of 951 < 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 >
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6501309 Semiconductor device having timing stabilization circuit with overflow detection function  
A semiconductor device includes an input buffer buffering an external clock signal to supply an internal clock signal. The semiconductor device further includes a timing-stabilization circuit which...
6498524 Input/output data synchronizing device  
Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a...
6493829 Semiconductor device enable to output a counter value of an internal clock generation in a test mode  
In a SDRAM, a switch circuit is provided between a memory circuit and a data output circuit. The switch circuit provides data read out from the memory circuit to the data output circuit in a normal...
6492852 Pre-divider architecture for low power in a digital delay locked loop  
A delay locked loop circuit for conserving power on a semiconductor chip is provided. The circuit includes a delay chain circuit responsive to a clock input signal for generating an output clock...
6489822 Delay locked loop with delay control unit for noise elimination  
Disclosed is a delay locked loop (DLL) for use in a semiconductor memory device, which has the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. The DLL...
6489820 Method and apparatus for distributing clocks  
Insertion delay associated with receiving and distributing a clock within an IC is removed using a DLL. The structure of a differential receiver in the feedback circuit of the DLL is substantially...
6489824 Timing-control circuit device and clock distribution system  
A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin...
6489823 Semiconductor device capable of generating highly precise internal clock  
A DLL circuit includes a delay line having a configuration with delay stages receiving alternate complementary clock signals ECK and /ECK having an adjusted phase difference therebetween. A...
6476653 DLL circuit adjustable with external load  
The present invention provides a DLL circuit performing a phase adjustment in accordance to an output load, and capable of adjusting the phase in a shot time. In the present invention, in a delayed...
6469555 Apparatus and method for generating multiple clock signals from a single loop circuit  
A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the...
6466069 Fast settling charge pump  
This invention provides a charge pump biasing circuit that varies the bias when the phase lock loop changes frequency to improve the settling time of the phase lock loop. During a frequency change,...
6459312 Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop  
The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a...
6459314 Delay locked loop circuit having duty cycle correction function and delay locking method  
A delay locked loop circuit having a duty cycle correction function and a delay locking method are provided. The delay locked loop circuit includes a delaying portion for generating a first output...
6456129 Internal clock signal generator  
A stable internal clock signal generator capable of suppressing an oscillation caused by a fluctuation in a power source or the like. A shift register 14 stores a binary comparison result...
6456130 Delay lock loop and update method with limited drift and improved power savings  
A delay lock loop circuit, in accordance with the present invention includes a delay lock loop unit having a power down mode. The delay lock loop unit includes a delay line having an input and an...
6452432 Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same  
A signal processing circuit includes a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a...
6452430 Phase-locked loop circuit  
MOS devices are added respectively to each stage of the voltage-controlled oscillator in a phase-locked loop circuit for improving the operating frequency range and the stability of middle/low...
6448756 Delay line tap setting override for delay locked loop (DLL) testability  
An integrated circuit having a delay locked loop (DLL) connected to a test circuit. The DLL includes a plurality of taps connected to a plurality of register cells. The test circuit is capable of...
6448826 Semiconductor device incorporating circuit for generating control clock in accordance with external clock frequency  
A semiconductor device according to the present invention operates in response to a control clock generated by a control clock generating circuit. The control clock generating circuit includes a...
6445232 Digital clock multiplier and divider with output waveform shaping  
A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency...
6445229 Digital phase lock loop  
A clock multiplier ( 40 ) comprises a digital phase lock loop circuit having a single variable delay stage ( 44 ) for generating high and low phases for the output clocks. The variable delay stage...
6441657 Combinational delay circuit for a digital frequency multiplier  
A combination delay circuit for use in a frequency multiplier comprises a first delay circuit including a plurality of delay lines each having eight segments each effecting a unit delay time t d ,...
6437617 Method of controlling a clock signal and circuit for controlling a clock signal  
A method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T 1 −T 2 ) wherein T 1 is a cycle of the...
6437618 Delay locked loop incorporating a ring type delay and counting elements  
Disclosed is a delay locked loop for use in a semiconductor memory device, for operating in low clock frequency applications that require a small chip size. The delay locked loop includes an input...
6437616 Delay lock loop with wide frequency range capability  
A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase...
6433597 Delay locked loop with reduced noise response  
A delay locked loop is disclosed which is less responsive to noise so as to improve an AC parameter tAC. The delay locked loop generally includes: a phase detector, a shift register, and a noise...
6429693 Digital fractional phase detector  
A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation...
6429715 Deskewing clock signals for off-chip devices  
An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree,...
6424184 FREQUENCY-VOLTAGE CONVERSION CIRCUIT, DELAY AMOUNT JUDGEMENT CIRCUIT, SYSTEM HAVING FREQUENCY-VOLTAGE CONVERSION CIRCUIT, METHOD OF ADJUSTING INPUT/OUTPUT CHARACTERISTICS OF FREQUENCY-VOLTAGE CONVERSION CIRCUIT, AND APPARATUS FOR AUTOMATICALLY ADJUSTING INPUT  
A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IV dd in accordance with the frequency of the clock as an output. The input and output...
6424193 Circuit for synchronizing frequencies of clock signals  
A phase-locked loop (PLL) circuit delays an input clock signal having a first frequency and generates a feedback signal to be delayed with respect to the input clock signal by one cycle. After...
6417705 Output driver with DLL control of output driver strength  
An output driver includes an adjustable main output stage and a control circuit with a digital delay locked loop (digital DLL) circuit and an adjustable scaled output stage. The main output stage...
6417706 Internal clock generator generating an internal clock signal having a phase difference with respect to an external clock signal  
An internal clock generation circuit according to the present invention comprises a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and...
6417714 Method and apparatus for obtaining linear code-delay response from area-efficient delay cells  
An area-efficient delay cell utilizes transistor stacks to control positive feedback responsive to a counter code, thereby controlling the hysteresis and overall signal delay of the cell. The...
6414526 Delay-locked loop circuit  
A delay-locked loop circuit (DLL) includes a delay line with a delay which can be varied in a controlled manner to delay a periodic input signal having a period T, and a control circuit for...
6414527 Semiconductor device replica circuit for monitoring critical path and construction method of the same  
A semiconductor device provided with a replica circuit functioning as an equivalent circuit to that of a path configuration selected as a critical path in the semiconductor circuit and an...
6414528 Clock generation circuit, serial/parallel conversion device and parallel/serial conversion device together with semiconductor device  
A clock generation circuit that generates multi-phase output clock signals which immediately follow any change in the period of an input clock signal. This clock generation circuit comprises a...
6407601 Delay cell  
A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled...
6404248 Delay locked loop circuit for synchronizing internal supply clock with reference clock  
A DLL circuit has edge detecting/phase comparing portion 2 that generates an original comparison signal that is set to logic “1” when the rise-up of feedback clock FBCLK is prior to the rise-up...
6404247 All digital phase-locked loop  
An all-digital phase-locked loop is disclosed which comprises: (a) a digital control oscillator for receiving a local signal and generating an output signal to be locked in with an input signal,...
6396321 Semiconductor integrated circuit equipped with function for controlling the quantity of processing per unit time length by detecting internally arising delay  
A semiconductor integrated circuit 10 comprises an internal logic circuit 16 , a delay detecting circuit 11 which monitors changes in delay length within the semiconductor integrated circuit ...
6396322 Delay locked loop of a DDR SDRAM  
A delay locked loop is disclosed which is capable of operating at both of a rising edge and a falling edge of a clock. The delay locked loop includes: a first differential amplifier receiving a...
6392466 Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path  
A controllable pulse-clock-delay apparatus for use with an integrated circuit, the controllable pulse-clock-delay apparatus including an input pulse clock terminal that is adapted to receive an...
6392458 Method and apparatus for digital delay locked loop circuits  
The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three...
6389090 Digital clock/data signal recovery method and apparatus  
For a digital communications receiver, a clock and data signal recovery circuit and method use an all digital delay locked loop timed by an on-chip transmit clock signal. The digital delay locked...
6388482 DLL lock scheme with multiple phase detection  
A delay lock loop, in accordance with the present invention, includes a plurality of phase detectors each receiving a first clock signal and a second clock signal. Each phase detector includes a...
6389091 Digital phase locked loop capable of suppressing jitter  
A digital phase locked loop keeps an output signal exactly in phase and frequency with a reference signal. An oscillator has a plurality of delay elements which are connected to one another in a...
6377092 Delay locked loop circuit capable of adjusting phase of clock with high precision  
A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output...
6377100 Semiconductor device  
A semiconductor device, comprising a stabilized timing circuit for regulating the phase of each of first and second clocks complementary with each other input from an external source and generating...
6373303 Sync signal generating circuit provided in semiconductor integrated circuit  
A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a...
6373308 Direct-measured DLL circuit and method  
A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the...
Matches 651 - 700 out of 951 < 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 >