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6844761 DLL with false lock protector  
A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between...
6845459 System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines  
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and...
6842057 Analog state recovery technique for DLL design  
A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is...
6839301 Method and apparatus for improving stability and lock time for synchronous circuits  
Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase...
6838917 Circuit configuration for processing data, and method for identifying an operating state  
A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter...
6836165 DLL circuit and method of generating timing signals  
A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied...
6836153 Systems and methods for phase detector circuit with reduced offset  
Systems and methods for synchronizing a system clock signal with a reference clock signal having a reduced phased offset to improve operating speeds of integrated circuits. This is accomplished by...
6836166 Method and system for delay control in synchronization circuits  
A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having...
6831492 Common-bias and differential structure based DLL  
A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit,...
6828835 Delay locked loop circuit interoperable with different applications  
A new Delay Locked Loop (DLL) circuit is interoperable with products having different applications by controlling the count of a DLL circuit according to the operating clock frequency. Therefore,...
6825703 Delay locked loop and method of driving the same  
Disclosed are a delay locked loop (DLL) and a method of driving the same. The delay locked loop includes a clock buffer for buffering an inputted external clock to generate an internal clock, the...
6825644 Switching power converter  
A switching power converter including a ring oscillator constructed using a plurality of series connected inverters is utilized to generate a plurality of waveforms. A selection circuit, in...
6819153 Semiconductor device for clock signals synchronization accuracy  
A semiconductor device that generates a clock which is synchronized with a reference signal stably and with fixed synchronization accuracy, and enables to deal with an abrupt variation in the...
6819190 Robust fractional clock-based pulse generator for digital pulse width modulator  
A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to...
6815990 Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same  
DLL integrated circuits include least one delay element associated with the generation of an internal clock signal and a control circuit that is configured to periodically adjust a delay of said at...
6815989 Sequential activation delay line circuits and methods  
Delay line circuits and methods include a series of unit delay cells, a respective one of which includes an input and an output that are sequentially connected such that an output of a preceding...
6815986 Design-for-test technique for a delay locked loop  
A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for...
6812757 Phase lock loop apparatus  
A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the...
6812758 Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators  
A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses...
6812753 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal  
A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled...
6812759 DLL circuit capable of preventing locking in an antiphase state  
A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed...
6809602 Multi-mode VCO  
A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic...
6809601 Phase detector for a delay locked loop and delay locked loop with the phase detector  
A phase detector for a delay locked loop with a delay unit that delays a periodic clock signal by a settable delay, has a first input for the periodic clock signal, a second input for the delayed...
6803797 System and method for extending delay-locked loop frequency application range  
A delay-locked loop includes an override controller for controlling the frequency range within which the loop operates. The override controller controls this range based on the output of a detector...
6798303 Clock signal generating device  
A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished by the fact that a phase shifting...
6794912 Multi-phase clock transmission circuit and method  
A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the...
6794913 Delay locked loop with digital to phase converter compensation  
A delay locked loop circuit 300 consistent with certain embodiments of the present invention has a delay line 304 with coarse adjustment 322 and fine adjustment 360 inputs. The coarse...
6791380 Universal clock generator  
The present invention discloses a universal clock generator, which comprises a high frequency clock region for generating high frequency clocks and a low frequency clock region for generating high...
6791420 Phase locked loop for recovering a clock signal from a data signal  
A phase locked loop for recovering a clock signal from a data signal including a delay locked loop with a nonlinear digital phase detector. The delay locked loop that is embedded in the phase...
6791384 Delay adjustment circuit for delay locked loop  
A delay adjustment circuit for a delay locked loop, comprises a delay rough adjustment circuit unit (to which input clock signal CLK-IN, and delay control signals A 1 to A 6 are transmitted) for...
6788119 Delay line circuit providing clock pulse width restoration in delay lock loops  
Delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature, and programmable delay circuits that enable the DLLs. A DLL can include optional...
6788754 Method and apparatus for de-skewing clock edges for systems with distributed clocks  
The present invention relates to a system and method for adaptively adjusting delays along selected signal paths in order to equalize the signal delays at various distributed points within an...
6784714 Digital phase control using first and second delay lines  
A digital phase control method phase shifts a predetermined number of clock signals having the same frequency and having different phases at high precision and at high resolution as a whole with...
6784707 Delay locked loop clock generator  
A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal,...
6777990 Delay lock loop having an edge detector and fixed delay  
A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first...
6774691 High resolution interleaved delay chain  
An improved delay chain for use in a delay locked loop which provides smooth phase adjustment and high resolution. In a delay chain having a series of cascaded unit delay elements, the outputs of a...
6775342 Digital phase shifter  
After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the...
6774687 Method and apparatus for characterizing a delay locked loop  
A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and...
6774689 Triple input phase detector and methodology for setting delay between two sets of phase outputs  
An improved clock generation circuit using a multi-phase phase-locked loop (PLL) circuit design that incorporates a dual set of PLLs. A first PLL maintains frequency lock control of an oscillator...
6774690 Digital dual-loop DLL design using coarse and fine loops  
A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine...
6774686 Method for minimizing jitter using matched, controlled-delay elements slaved to a closed-loop timing reference  
A method for minimizing jitter using substantially matched, controlled, delay elements is disclosed. The method includes generating an internal loop-timing reference, and controlling elements...
6774688 Circuit for synchronizing signals during the exchange of information between circuits  
A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay...
6774693 Digital delay line with synchronous control  
A digital delay line, which includes a plurality of multiplexer delay elements, arranged in sequence with each of the plurality of multiplexer delay elements having an associated control input. A...
6768360 Timing signal generation circuit and semiconductor test device with the same  
A timing signal generation circuit comprising: a negative feedback loop comprising; a variable delay circuit for outputting a timing signal delayed from an input clock signal by a delay amount...
6768361 Clock synchronization circuit  
A clock synchronization circuit using a phase mixer is disclosed. The clock synchronization circuit generates an internal clock signal having a phase between phases of two clock signals generated...
6768356 Apparatus for and method of implementing time-interleaved architecture  
In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved...
6765976 Delay-locked loop for differential clock signals  
A significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to...
6766464 Method and apparatus for deskewing multiple incoming signals  
An apparatus and method for compensating skew across a plurality of data interfaces includes using a recovered clock signal at an incoming clock rate to regulate output from a deskew interface. The...
6765419 Dynamic delay line control  
A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward...
6762633 Delay locked loop circuit with improved jitter performance  
A delay locked loop circuit with a novel structure for improving a jitter performance is disclosed. The delay locked loop circuit includes a delay circuit for receiving an input clock signal and...
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