Matches 451 - 500 out of 951 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >
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6956416 Powerup control of PLL  
An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase...
6956442 Ring oscillator with peaking stages  
A ring oscillator with a plurality of delay stages having selectable active loads for selecting an R-C time constant that defines a delay through the delay stage. The ring oscillator oscillation...
6956418 Delay locked loop device  
A delay locked loop device includes a first delay line for receiving an external clock signal and a first delay control signal to generate a first internal clock signal; a second delay line for...
6954095 Apparatus and method for generating clock signals  
A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the...
6954093 Clocking scheme and clock system for a monolithic integrated circuit  
Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c 0 ) generated by a clock source which is coupled to N intermediate clocks (c 1 through cN) which are delayed...
6954094 Semiconductor memory device having partially controlled delay locked loop  
A semiconductor memory device having a partially controlled delay locked loop includes a delay locked loop and a control signal generator. The control signal generator generates a first control...
6952138 Generation of a phase locked loop output signal having reduced spurious spectral components  
The present invention helps to mitigate and reduce the amount of interfering signals (e.g. RF leakage) that enter the phase detector of a phase locked loop by acting as a less than perfect sampler....
6952123 System with dual rail regulated locked loop  
An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit...
6949966 DLL circuit capable of preventing malfunctioning causing locking in an antiphase state  
A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed...
6946887 Phase frequency detector with programmable minimum pulse width  
A structure and associated method for reducing a static phase error in a phase-locked loop circuit. The phase-locked loop circuit comprises a voltage controlled oscillator and a phase frequency...
6946888 Percent-of-clock delay circuits with enhanced phase jitter immunity  
DLL integrated circuits include least one delay element associated with the generation of an internal clock signal and a control circuit that is configured to periodically adjust a delay of said at...
6944833 Delay model circuit for use in delay locked loop  
A delay model circuit for use in a delay locked loop (DLL) of a semiconductor device. The delay model circuit includes a first delay circuit for providing a first delay amount; a second delay...
6943608 Wide frequency range voltage-controlled oscillators (VCO)  
A structure for a delay cell in a Voltage-Controlled Oscillators (VCO) and method for operating the delay cell. The delay cell comprises a latch and an impedance circuit (comprising resistance and...
6943601 Method and device for phase detection  
A phase detection system is used in particular in a Delay-Locked Loop (DLL) to generate, as a function of phase differences of different signals ( 1, 2, 3 ), at least one control signal for...
6943602 Delay locked loop and locking method thereof  
The present invention provides a delay locked loop of a semiconductor memory device for preventing a stuck fail. The DLL of the present invention includes: a buffer for outputting a first clock...
6940325 DLL circuit  
A DLL circuit synchronizes an external input clock applied from an outside of a system with an internal input clock used inside the system using a divider unit. The DLL circuit includes a detection...
6937076 Clock synchronizing apparatus and method using frequency dependent variable delay  
A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate...
6937530 Delay locked loop “ACTIVE Command” reactor  
A delay locked loop (DLL) that applies an amount of delay to an external clock signal to generate multiple delayed signals. One of the delayed signals is selected as an internal clock signal. The...
6933757 Timing method and apparatus for integrated circuit device  
According to one embodiment, a timing circuit ( 300 ) can include a first control circuit ( 302 ), a first clocked circuit ( 304 ), a second clocked circuit ( 306 ), and a second control circuit (...
6930524 Dual-phase delay-locked loop circuit and method  
A delay-locked loop includes a clock multiplier that generates a multiplied clock signal responsive to an input clock signal. The multiplied clock signal has a frequency that is a multiple of a...
6927611 Semidigital delay-locked loop using an analog-based finite state machine  
A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a...
6928128 Clock alignment circuit having a self regulating voltage supply  
Clock alignment circuits and techniques for reducing power dissipation, increasing power supply noise immunity, decreasing process and temperature variation sensitivity, and providing a wide...
6924680 DLL circuit for stabilization of the initial transient phase  
A DLL circuit for phase matching of a periodic input signal, having a variable delay unit, having a delay element and having a regulation unit which has a regulation device, for setting an input...
6924679 Power supply control device, semiconductor device and method of driving semiconductor device  
A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a...
6919745 Ring-resister controlled DLL with fine delay line and direct skew sensing detector  
The present invention related to a ring-resister controlled DLL with fine delay line and a direct skew sensing detector, which is applicable to circuitry for compensating skew between external and...
6917229 Delay locked loop having low jitter in semiconductor device  
A DLL circuit having a low jitter in a semiconductor device, includes a delay model unit for compensating a time difference between an external clock signal and an internal clock signals and...
6917230 Low pass filters in DLL circuits  
Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a...
6912380 PLL circuit and wireless mobile station with that PLL circuit  
In a PLL circuit, and a wireless mobile station with that PLL circuit, an LPF charging constant current source, a discharging constant current source and a high-speed charging constant current...
6911851 Data latch timing adjustment apparatus  
In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to...
6909311 Methods and apparatus for synthesizing a clock signal  
One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay...
6903586 Gain control circuitry for delay locked loop circuit  
A delay locked loop (DLL) circuit having gain control is presented. The DLL circuit includes a bias generator responsive based on an error signal to produce first and second bias voltages to...
6900678 Delay lock circuit using bisection algorithm and related method  
A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes...
6900679 Digital phase control circuit  
The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL 1 in which differential buffers G 1 -G 10 having a propagation delay time of 160 ps...
6897693 Delay locked loop for improving high frequency characteristics and yield  
A delay locked loop (DLL) is provided that generates an internal clock signal in synchronization with an external clock signal. First through third amplifiers convert the swing width of the...
6891416 Timing generation circuit and method for timing generation  
A timing generation circuit includes: a delay section including a plurality of delay circuits for sequentially transferring a clock signal therethrough, wherein the clock signal is delayed by a...
6891415 Method and apparatus for enabling a timing synchronization circuit  
A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to receive an input clock signal and delay the...
6885228 Non-iterative signal synchronization  
Non-iterative signal synchronization is disclosed. A system of one embodiment of the invention has a provider and a mechanism. The provider provides two signals. The mechanism non-iteratively...
6882229 Divide-by-X.5 circuit with frequency doubler and differential oscillator  
A divide by X.5 circuit can be implemented as a divided by 1.5 circuit. A phase-locked loop (PLL) has a quadrature voltage-controlled oscillator (VCO) that generates four phases offset at 0, 90,...
6879188 Semiconductor integrated circuit device  
A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock...
6876240 Wide range multi-phase delay-locked loop  
A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay...
6870411 Phase synchronizing circuit  
An object of this invention is to provide a phase synchronizing circuit capable of automatically adjusting a VCO such that the VCO satisfies a predetermined frequency range even in a frequency...
6867627 Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics  
Delay-locked loops have high bandwidth locking characteristics that are less susceptible process, voltage and temperature (PVT) variations. These DLLs are configured to support transition from a...
6861883 Semiconductor integrated circuit for phase management of clock domains including PLL circuit  
Assuming that clocks in an A clock driver ( 102 ), a B clock driver ( 103 ) and a CMOS buffer circuit ( 119 ) have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a...
6861886 Clock deskew protocol using a delay-locked loop  
A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed...
6859078 Delay lock loop circuit  
A delay lock loop circuit includes a reference loop for receiving an external clock signal and for generating a second output signal and a first output signal which includes a plurality of signals...
6850583 Clock generation apparatus  
A clock generation apparatus generates a synchronous clock based on an input analog signal. The average of maximum and minimum values of a digital signal in a predetermined period is used as a...
6847242 Escalator code-based delay-locked loop apparatus and corresponding methods  
A delay-locked loop (DLL) may include: a variable delay line arrangement operable to receive a reference clock and to output a delayed local clock; a phase comparator device operable to compare...
6847241 Delay lock loop using shift register with token bit to select adjacent clock signals  
Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single...
6845458 System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines  
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and...
6844766 VCDL with linear delay characteristics and differential duty-cycle correction  
A voltage-controlled delay line (VCDL) comprises a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells. A...
Matches 451 - 500 out of 951 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >