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7403073 Phase locked loop and method for adjusting the frequency and phase in the phase locked loop  
A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a...
7402821 Application of digital frequency and phase synthesis for control of electrode voltage phase in a high-energy ion implantation machine, and a means for accurate calibration of electrode voltage phase  
An improved HE LINAC-based ion implantation system is disclosed utilizing direct digital synthesis (DDS) techniques to obtain precise frequency and phase control and automated electrode voltage...
7400182 Clock generator with one pole and method for generating a clock  
A clock generator based on a phase-locked loop with one pole and an improved period jitter characteristic is disclosed. The clock generator comprises a phase detector for generating a phase...
7397882 Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion  
A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if...
7397881 Erroneous phase lock detection circuit  
The present invention is concerned with a phase comparator circuit and provides an erroneous phase lock detection circuit that detects erroneous phase lock occurring when the duty cycle of data...
7397880 Synchronization circuit and synchronization method  
In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the...
7397313 Auto-gain controlled digital phase-locked loop and method thereof  
A digital PLL system includes a first multiplier coupled to a phase difference signal for multiplying the phase difference signal by a first gain factor; a second multiplier coupled to the phase...
7394323 PLL frequency synthesizer  
A PLL frequency synthesizer improves near C/N, shortens lockup time, and reduces residual FM. In this apparatus, an input current signal is converted to a voltage signal by one of a plurality of...
7394320 Phase-locked loop and method for operating a phase-locked-loop  
A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a...
7391839 Accumulator based phase locked loop  
There is disclosed a phase locked loop comprising: a phase frequency detector for receiving as a first input a reference signal and for generating a control signal; a voltage controlled oscillator...
7391270 Phase locked loop and method for phase correction of a frequency controllable oscillator  
A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an...
7391244 Delay-locked loop  
This invention relates to a delay locked loop comprising a line of delay cells (R 1 , R 2 , . . . , Rn) mounted in series, the delay signal output by the loop being output from the output of one of...
7391243 Low power and low timing jitter phase-lock loop and method  
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase...
7388441 Robust phase-lock detector  
A robust phase-lock detector for a phase-locked loop examines both the sum frequency and baseband components of an error signal from the phase-locked loop to determine that both a reference signal...
7388415 Delay locked loop with a function for implementing locking operation periodically during power down mode and locking operation method of the same  
A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock...
7388412 Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock  
A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The...
7385432 Commutating phase selector  
A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input...
7382169 Systems and methods for reducing static phase error  
In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output...
7382163 Phase frequency detector used in digital PLL system  
A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a...
7375563 Duty cycle correction using input clock and feedback clock of phase-locked-loop (PLL)  
A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop...
7375562 Phase locked system for generating distributed clocks  
A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the...
7375557 Phase-locked loop and method thereof and a phase-frequency detector and method thereof  
The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input...
7375553 Clock tree network in a field programmable gate array  
A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a...
7372932 Locking-status judging circuit for digital PLL circuit  
A locking-status judging circuit is composed of a comparator that compares a phase error signal with a reference signal for judging whether or not a digital PLL circuit locks on an input signal and...
7372341 Noise immunity circuitry for phase locked loops and delay locked loops  
A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to...
7372340 Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages  
A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a...
7372337 Voltage controlled oscillator comprising an injection pulling compensation circuit  
The present invention relates to a method for stabilising the operation of a voltage controlled oscillator driven by a phase locked loop, the voltage controlled oscillator delivering an RF signal...
7372311 Delay locked loop for controlling duty rate of clock  
There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second...
7368962 Clock supply device  
Each clock supply unit comprises an inter-unit synchronization portion which operates when the clock supply unit is acting as a standby unit, using a clock signal from a DPLL of a unit which is...
7368961 Clock distribution network supporting low-power mode  
A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock...
7368954 Phase comparison circuit and CDR circuit  
Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator...
7365607 Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL)  
A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the...
7365581 Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL  
A PLL/DLL circuit is current self-biased responsive to a current I ld provided from a voltage regulator to a VCO or VCDL. Bias current I bias , which is proportional to I ld , is provided to...
7365580 System and method for jitter control  
A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of...
7362151 Timing circuits with improved power supply jitter isolation technical background  
In accordance with the invention, feed forward compensation of jitter induced by power supply noise is incorporated into the negative feedback control loop of a timing synchronization circuit, such...
7358783 Voltage, temperature, and process independent programmable phase shift for PLL  
A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field...
7356111 Apparatus and method for fractional frequency division using multi-phase output VCO  
A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer...
7355922 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM  
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a...
7355462 Phase lock loop and method for operating the same  
A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for...
7352297 Method and apparatus for efficient implementation of digital filter with thermometer-code-like output  
A technique is disclosed for processing a binary coded signal to generate a thermometer coded signal. Such technique includes the following steps. A binary coded input signal is obtained. A binary...
7352253 Oscillator circuit with tuneable signal delay means  
The invention discloses an oscillator circuit ( 100, 200, 300, 400 ), comprising an oscillating element ( 110, 210, 310, 410 ) and output means ( 115, 215, 315, 415 ) for outputting an oscillation...
7352218 DLL circuit and method of controlling the same  
A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external...
7352217 Lock phase circuit  
Systems and techniques for producing a signal with a known phase relationship to a source clock at an output of an indeterminate circuit element such as a clock divider. The systems and techniques...
7348818 Tunable high-speed frequency divider  
A locking range of a current mode logic (CML) frequency divider circuit is tunable by dynamically adjusting a tail current of the frequency divider circuit according to a control signal. The...
7345515 Low power and low timing jitter phase-lock loop and method  
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase...
7342426 PLL with controlled VCO bias  
In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock....
7336755 PLL with low phase noise non-integer divider  
A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an...
7336752 Wide frequency range delay locked loop  
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a...
7336731 Demodulator with phase-adjusting function  
A demodulator with a phase-adjusting function including a detector including a delay detector delaying an input signal in delaying stages using a first clock obtained by frequency-dividing a...
7336559 Delay-locked loop, integrated circuit having the same, and method of driving the same  
A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured...
Matches 1 - 50 out of 1475 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >