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7161399 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
System and method to improve the efficiency of synchronous mirror delays and delay locked loops  
A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed....
7158603 Method and apparatus for compensating deviation variances in a 2-level FSK FM transmitter  
A dual-port voltage control oscillator for use in a frequency synthesizer has first and second input ports and an output. The first port is coupled in a phase-locked-loop configuration for...
7158602 Phase locked loop circuit and clock reproduction circuit  
A phase locked loop circuit and a clock reproduction circuit can operate stably with satisfying both of wide lock range and good jitter characteristics. The phase locked loop circuit for generating...
7158443 Delay-lock loop and method adapting itself to operate over a wide frequency range  
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line...
7154311 Delay locked loop in semiconductor memory device and locking method thereof  
Provided is a delay locked loop (DLL) adapted for high-speed operation of a semiconductor memory device. The delay locked loop (DLL) includes: a clock buffer; a plurality of clock dividers; and a...
7151814 Hogge phase detector with adjustable phase output  
A system and method are provided for adjusting the phase output of a Hogge phase detector. The method comprises: using a Hogge phase detector, generating a reference signal; using the Hogge phase...
7151399 System and method for generating multiple clock signals  
A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and...
7149270 Clock recovery circuit  
A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase locked loop circuit operating in a fast...
7148764 Communication semiconductor integrated circuit device and a wireless communication system  
In a communication semiconductor integrated circuit device, an oscillator (VCO 10 ) of a PLL circuit can operate in a plurality of frequency bands. With a control voltage (Vc) of the oscillator...
7148757 Charge pump-based PLL having dynamic loop gain  
A charge pump-based PLL dynamically controls loop gain in response to the frequency of an input signal. The loop gain is dynamically adjusted by varying the bias current of the charge pump circuit...
7148755 System and method to adjust voltage  
A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock...
7148753 Method and apparatus for generating a clock signal in holdover mode  
A first phase-locked loop circuit that includes a crystal oscillator, receives a reference clock signal and supplies a first phase-locked loop output signal based on the reference clock during...
7145975 Digital phase-locked loop compiler  
A digital phase-locked loop compiler includes a pre-divider, a phase digital converter, a digital-to-analog voltage converter, a voltage-control oscillator, a high-frequency oscillator, a...
7145400 Phase locked loop with a switch capacitor resistor in the loop filter  
A filter couples an output of a phase detector to an input of a voltage controlled oscillator. The filter has a first capacitor and a switch capacitor resistor that is in series with the first...
7142624 Analog unidirectional serial link architecture  
The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting...
7142025 Phase difference detector, particularly for a PLL circuit  
A phase difference detector adapted to generating a signal indicative of a phase difference between a first signal and a second signal, comprising: a first bistable element clocked by the first...
7141961 Method and device for generating clock signal  
A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators....
7139210 Synchronous semiconductor memory device for reducing power consumption  
A semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state...
7137022 Timing adjustment circuit and semiconductor device including the same  
In order to compare a phase of an internal clock signal outputted from a clock driver with that of a data strobe signal from a data strobe output circuit driven by the internal clock signal, a...
7136799 Mixed signal delay locked loop characterization engine  
A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop...
7136109 Self-adjusting pixel clock and method therefor  
A pixel clock generating circuit is provided in which a digital circuit generates a first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired...
7135901 Data recovery device using a sampling clock with a half frequency of data rate  
A data recovery device using a sampling clock with a half frequency of data rate is disclosed, which includes a phase detection circuit, a charge pump and a double clock frequency oscillation...
7132897 Method and circuit for producing a control voltage for a VCO  
The control voltage for a VCO (voltage controlled oscillator) is produced in a phase locked loop which in turn is controlled by a computer ( 40 ) including an integrated analog circuit ( 42 )....
7132895 Digitally-controlled oscillator  
A digitally-controlled oscillator comprises an input for the supply of a digital input word, an adder, a stable local oscillator and a delay circuit, comprising a delay stage with a number of...
7132864 Method for configuring multiple-output phase-locked loop frequency synthesizer  
A method is provided to configure a multiple-output phase-locked loop frequency synthesizer based upon a desired set of output frequencies. The method includes an act of selecting a candidate...
7129800 Compensation technique to mitigate aging effects in integrated circuit components  
A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple...
7129793 Device for calibrating the frequency of an oscillator, phase looked loop circuit comprising said calibration device and related frequency calibration method  
A device calibrates the frequency of an oscillator. The oscillator has first and second inputs and generates an output frequency responsive to a first voltage signal at the first input. The...
7129789 Fast locking method and apparatus for frequency synthesis  
A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal,...
7126430 PLL circuit  
The frequency of a first voltage controlled oscillator is stabilized in a first PLL circuit part into which a reference frequency signal is inputted. In addition, a second PLL circuit part is...
7126392 Semiconductor integrated device having reduced jitter and reduced current consumption  
A structure is provided for significantly reducing the current excessively consumed for generating a high-speed clock signal necessary for signal processing, and significantly improve the jitter...
7123065 Method of improving lock acquisition times in systems with a narrow frequency range  
The present invention adds an additional feedback loop to a phase locked loop (PLL). The additional feedback loop detects if the actual output frequency of the PLL is above or below the desired...
7120217 Phase-locked loop circuit  
In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and...
7119590 Scalable integrated circuit architecture  
An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an...
7119589 Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof  
A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to...
7116145 Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof  
A phase-locked loop circuit including a lock detection function is disclosed. The phase-locked loop circuit comprises a lock detection circuit. The lock detection circuit includes a...
7116144 High bandwidth phase locked loop (PLL)  
A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a...
7110486 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method  
A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of...
7109765 Programmable phase shift circuitry  
A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field...
7109764 PLL clock signal generation circuit  
A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is...
7109763 Phase locked loop operable over a wide frequency range  
A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The...
7106113 Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver  
An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment...
7103130 Phase-locked loop circuit  
Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency...
7102447 XO-buffer robust to interference  
Disclosed are methods and circuit configurations for reference frequency signal distribution circuitry that suppress unwanted spurious components introduced by way of RF signal leakage. The methods...
7102399 Low-noise frequency divider  
A multi-modulus divider for producing a low-noise divided output, wherein one embodiment comprises a low-noise frequency divider comprising a pulse-swallow configured divider module and first,...
7102398 Circuit for two PLLs for horizontal deflection  
A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output...
7098709 Spread-spectrum clock generator  
This invention provides a clock generator which is capable of improving modulation accuracy without accompanying an increase in consumption current by steady current when spectrum spread of a clock...
7098707 Highly configurable PLL architecture for programmable logic  
A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is...
7095816 Clock/data recovery circuit  
A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of...
7095289 Yank detection circuit for self-biased phase locked loops  
An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge...
7095260 Spread spectrum clock generation circuit, jitter generation circuit and semiconductor device  
A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock...
Matches 201 - 250 out of 1492 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >