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7634749 Skew insensitive clocking method and apparatus  
A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to...
7629816 Method and apparatus for pre-clocking  
A method and apparatus for pre-clocking have been disclosed. In one case pre-clocking is used to effectively decrease the delay to output timing with respect to a clock. In another case...
7622946 Design structure for an automatic driver/transmission line/receiver impedance matching circuitry  
A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL)...
7622974 Semiconductor device  
A semiconductor integrated circuit apparatus includes a periodic signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodic signal. The...
7619451 Techniques for compensating delays in clock signals on integrated circuits  
Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a...
7620136 Clock and data recovery circuit having gain control  
A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to...
7605620 System and method to improve the efficiency of synchronous mirror delays and delay locked loops  
A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed....
7605624 Delay locked loop (DLL) circuit for generating clock signal for memory device  
A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock...
7602223 Delay-locked loop circuit and method of generating multiplied clock therefrom  
A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling...
7590212 System and method for adjusting the phase of a frequency-locked clock  
A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an...
7576576 Switchable PLL circuit  
An electronic circuit includes a first and a second PLL stage (PLL 1 , PLL 2 ) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input...
7567640 Phase offset tracking method for tracking a phase offset and device thereof  
The invention relates to a phase offset tracking module and method for tracking a phase offset, and in particular, to a phase offset tracking module and method for tracking a phase offset in a...
7561652 High frequency spread spectrum clock generation  
For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is...
7545900 Low jitter and/or fast lock-in clock recovery circuit  
An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a...
7528638 Clock signal distribution with reduced parasitic loading effects  
Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock signal. A delay-locked loop (DLL)...
7525364 Delay control circuit  
A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the...
7499511 Clock recovery systems and methods for adjusting phase offset according to data frequency  
A clock recovery system includes a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal. A phase...
7495488 Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same  
A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital...
7492850 Phase locked loop apparatus with adjustable phase shift  
The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and...
7456673 Multi-phase clock generator  
Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a...
7447106 Delay stage-interweaved analog DLL/PLL  
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on...
7336110 Differential amplitude controlled sawtooth generator  
A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control...
7319728 Delay locked loop with frequency control  
A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals...
7317775 Switched deskew on arbitrary data  
A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and...
7301375 Off-chip driver circuit and data output circuit using the same  
An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data...
7295053 Delay-locked loop circuits  
A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase...
7227795 Data output circuit, data output method, and semiconductor memory device  
In a data output circuit, a data output method, and a semiconductor memory device, the data output circuit includes: an internal clock generation unit that delays an external clock signal by a...
7200451 Method for consistent on/off object to control radios and other interfaces  
In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware...
7190200 Delay locked loop capable of performing reliable locking operation  
A delay locked loop capable of performing a reliable locking operation is provided that includes a phase controller, which controls a phase of a reference clock signal in response to first and...
7164295 Feedback control system and method  
A feedback control system and method thereof are provided. The feedback control method includes (a) comparing the level of a reference signal with the levels of first and second signals, (b) if the...
7161400 Phase synchronization for wide area integrated circuits  
A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different...
7162000 Delay locked loop synthesizer with multiple outputs and digital modulation  
A delay locked loop circuit ( 200 ) in which multiple outputs are produced. A single delay line ( 24 ) is shared among multiple tap selection circuits ( 256 A, 265 B, 265 C). Fixed phase shifts (...
7138850 High-gain synchronizer circuitry and methods  
High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The...
7127022 Clock and data recovery circuits utilizing digital delay lines and digitally controlled oscillators  
Clock and data recovery (CDR) circuits that are fully digital. A data stream encoded with clocking information is passed through a tapped digital delay line. A phase and frequency detector coupled...
7120217 Phase-locked loop circuit  
In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and...
7116320 Display device, method of controlling the same, and projection-type display apparatus  
A liquid-crystal display device performs a feedback process. A video signal is written on pixels on a unit by unit basis, each unit including a plurality of pixels (six pixels, for example). Scan...
7110485 System and method for clock synchronization of multi-channel baud-rate timing recovery systems  
A clock control circuit for use in a multi-channel baud-rate timing recovery loop includes a control circuit responsive to a phase error signal from at least one phase detector for generating at...
7098708 Low-power direct digital synthesizer with analog interpolation  
An MN counter with analog interpolation (“MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and...
7073001 Fault-tolerant digital communications channel having synchronized unidirectional links  
A method of synchronizing or initiating channel lock in a serial loop formed by an initializing transceiver and subject transceivers disclosed. Should a transceiver in the serial loop detect that...
7042296 Digital programmable delay scheme to continuously calibrate and track delay over process, voltage and temperature  
The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay...
7016259 Apparatus for calibrating the relative phase of two reception signals of a memory chip  
A calibration apparatus is provided for adjusting the relative phase between two signals received at a memory chip, the two signals being generated such that they are synchronized with one another...
6999480 Method and apparatus for improving data integrity and desynchronizer recovery time after a loss of signal  
An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the...
6982578 Digital delay-locked loop circuits with hierarchical delay adjustment  
Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each...
6972603 Maximum time interval error test signal generating apparatus not affected by low-pass measuring filter  
An MTIE test signal generating apparatus generates a predetermined MTIE test signal. An MTIE measuring unit includes a low-pass measuring filter having a predetermined high-cut characteristic. A...
6973293 Apparatus and method for compensating for the offset of a mixer  
An apparatus and a method compare the output signal of a mixer in a detector with one of two input signals of the mixer, in order to compensate for the offset of a mixer or modulator. The detector...
6958635 Low-power direct digital synthesizer with analog interpolation  
An MN counter with analog interpolation (an “MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M...
6906555 Prevention of metastability in bistable circuits  
Methods and apparatus implementing techniques for prevention of metastability in a bistable circuit. The techniques include detecting a change in a data signal, sampling the detected change in...
6842398 Multi-mode synchronous memory device and methods of operating and testing same  
A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input...
6839301 Method and apparatus for improving stability and lock time for synchronous circuits  
Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase...
6829309 Phase detector for baud rate-sampled multi-state signal receiver  
The invention is related to analog to digital conversion of a multi-level analog signal at a very low sampling rate. The analog signal is sampled by a recovered clock to produce a succession of...
Matches 1 - 50 out of 190 1 2 3 4 >