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8179174 Fast phase locking system for automatically calibrated fractional-N PLL  
The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock...
8169242 Programmable fine lock/unlock detection circuit  
An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based...
8169241 Proportional phase comparator and method for phase-aligning digital signals  
Embodiments of a proportional phase comparator and method for aligning digital signals are generally described herein. In some embodiments, circuitry to align digital signals comprises a...
8170170 Carrier synchronizing circuit and carrier synchronizing method  
Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error...
8164366 Locked loops, bias generators, charge pumps and methods for generating control voltages  
Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator,...
8160123 Device for receiving satellite signals including a phase loop with delay compensation  
Described is a device for receiving radio-navigation signals by satellite, said received signals being transmitted at a carrier frequency. The device includes at least means for generating a local...
8159276 Method for using digital PLL in a voltage regulator  
A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from...
8159275 Phase-locked loop and bias generator  
A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a...
8155257 Synchronizing circuit and controlling method thereof  
Disclosed herein is synchronizing circuit including: a numerically controlled oscillating section; a phase rotating section; a phase error estimating section; a loop filter; and a gain controlling...
8149034 Delay lines, methods for delaying a signal, and delay lock loops  
Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of...
8149031 Duty-cycle feedback charge pump  
A charge pump includes a reference charge pump with an input interface to accept a phase detector signal and a duty-cycle feedback signal, and an output to supply a control voltage. A replica...
8149030 Clock generator to reduce long term jitter  
A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a...
8144756 Jitter measuring system and method  
The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for...
8140039 Quadrature-input quadrature-output divider and phase locked loop frequency synthesizer or single side band mixer  
The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the...
8139700 Dynamic quadrature clock correction for a phase rotator system  
A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature...
8139703 Data relay apparatus and semiconductor integrated circuit having the same  
A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock...
8134392 Phase locked loop  
A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated...
8134393 Method and apparatus for correcting phase offset errors in a communication device  
A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An...
8125253 System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes  
A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled...
8125254 Techniques for configuring multi-path feedback loops  
In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass...
8125255 PLL circuit  
Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout...
8121242 Frequency lock stability in device using overlapping VCO bands  
A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO...
8120988 Delay locked loop circuit for preventing failure of coarse locking  
A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and...
8120407 Techniques for varying phase shifts in periodic signals  
A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The...
8120395 Use of data decisions for temporal placement of samplers  
A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response...
8115527 PLL apparatus  
There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified...
8115526 PLL oscillator circuit  
Disclosed is a PLL oscillator circuit capable of examining an unlock state while being equipped with an auto retry function enabling automatic relock. In the PLL oscillator circuit, a MPU receives...
8116417 Deskewing method and apparatus, and data reception apparatus using the deskewing method and apparatus  
An up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions, wherein the data...
8115525 Frequency synthesizer  
There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset...
8111093 Power supply noise rejection in PLL or DLL circuits  
A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise...
8107582 Methods and apparatus for digital clock recovery  
A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency...
8106690 Semiconductor integrated circuit device  
To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator...
8106691 Phase adjustment circuit  
In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function ...
8102197 Digital phase locked loop  
An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a...
8102195 Digital phase-locked loop circuit including a phase delay quantizer and method of use  
A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit....
8102948 Carrier recovery apparatus and method thereof  
A carrier recovery apparatus includes a pilot strength detector, a first lock loop, a second lock loop, and a controller. The pilot strength detector determines whether a pilot strength of an input...
8102196 Programmable dual phase-locked loop clock signal generator and conditioner  
A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module...
8098787 Method and apparatus for precision quantization of temporal spacing between two events  
One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input...
8098786 Reception apparatus  
In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase...
8085070 Overclocking with phase selection  
A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is...
8081723 Serial data signal eye width estimator methods and apparatus  
Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first...
8076960 Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter  
A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first...
8067965 Clock and data recovery circuit with proportional path  
A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a...
8063677 Phase locked loop and method for operating the same  
A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay...
8063682 Semiconductor circuit for performing signal processing  
A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided...
8058915 Digital phase-locked loop and digital phase-frequency detector thereof  
A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating...
8058916 Lockstep synchronization and maintenance  
A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference...
8059777 Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter  
A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL)...
8054114 Fractional-N phase-locked loop  
A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed...
8050373 Phase interpolator based transmission clock control  
A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a...
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