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7613266 |
Binary controlled phase selector with output duty cycle correction
A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from...
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7606342 |
Tracking the phase of a received signal
The tracking of the phase of a received signal having a known preamble is accomplished by the steps of: initializing a phase-locked loop in accordance with estimated phase parameters, which are...
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7605631 |
Delay line synchronizer apparatus and method
A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains...
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7587014 |
Digital frequency/phase recovery circuit
A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a...
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7581128 |
Microcomputer selecting operating condition
A microcomputer includes a CPU, a program memory for storing a subroutine program, peripheral circuits, a clock circuit, and a voltage drop detection circuit. When the voltage drop detection...
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7573968 |
Data transmission circuit with serial interface and method for transmitting serial data
A data transmission circuit includes a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the...
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7571363 |
Parametric measurement of high-speed I/O systems
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
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7567101 |
Digital PLL circuit
A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has...
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7561652 |
High frequency spread spectrum clock generation
For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is...
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7558552 |
Integrated circuit and method of generating a bias current for a plurality of data transceivers
Various embodiments of the present invention relate to circuits for and methods of generating a bias current for a plurality of data transceivers on an integrated circuit. According to one...
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7555089 |
Data edge-to-clock edge phase detector for high speed circuits
A novel method and system for detecting and synchronizing the skew between a data signal and a reference clock signal are presented. A multiple-phase clock generator is used to create multiple...
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7554370 |
Method and system for synchronizing phase of triangular signal
A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular...
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7548099 |
Semiconductor device with delay section
In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value...
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7545168 |
Clock tree network in a field programmable gate array
A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a...
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7536617 |
Programmable in-situ delay fault test clock generator
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in...
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7515664 |
Method of recovering data in asynchronous applications
Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number...
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7515639 |
Asynchronous data transmitting apparatus
An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a...
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7515003 |
Filter-based lock-in circuits for PLL and fast system startup
All embodiments of the present invention basically include an upper transistor and a lower transistor connected in series between a power supply and ground. The upper transistor and the lower...
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7512848 |
Clock and data recovery circuit having operating parameter compensation circuitry
A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are...
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7512200 |
Circuit to detect clock delay and method thereof
Provided are a circuit and a method of detecting clock delay where the circuit to detect clock delay includes a delay detection circuit and a clock forwarding circuit, the delay detection circuit...
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7502433 |
Bimodal source synchronous interface
Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of...
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7499514 |
Communication system, reception apparatus and method, recording medium and program
A communication system, reception apparatus and method, recording medium and program are provided. A technique is provided wherein, even where means for synchronizing a reception clock with a...
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7499511 |
Clock recovery systems and methods for adjusting phase offset according to data frequency
A clock recovery system includes a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal. A phase...
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7495488 |
Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same
A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital...
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7492850 |
Phase locked loop apparatus with adjustable phase shift
The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and...
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7486753 |
Synchronization establishment circuit and synchronization establishment method
A terminal is wirelessly connected to a base station. The terminal has a timer and a controller. The timer has a register for storing a beacon interval as a comparison value. The timer also...
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7478256 |
Coordinating data synchronous triggers on multiple devices
System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media...
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7463096 |
Dynamic voltage and frequency management in integrated circuits
This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of...
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7453971 |
Sampling-error phase compensating apparatus and method thereof
A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals. The method sequentially includes: sampling each data...
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7447106 |
Delay stage-interweaved analog DLL/PLL
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on...
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7443938 |
Method and system for synchronization between transmitter and receiver in a communication system
A method and system for synchronization between a transmitter and a receiver in a communication system is provided. The receiver receives a plurality of signals from the transmitter. According to...
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7443217 |
Circuit and method to balance delays through true and complement phases of differential and complementary drivers
A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver...
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7439773 |
Integrated circuit communication techniques
An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level....
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7436919 |
Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface
Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams ( 106 ) with a common clock signal ( 116 ). Activity occurring in each bitstream is detected ( 304 ) for...
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7436906 |
Synchronous detector with high accuracy in detecting synchronization and a method therefor
In a symbol timing detector, a correlator calculates a correlation value for a received radio packet signal. A peak detector compares the correlation value with a threshold value to be used, and...
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7436904 |
Data recovery apparatus and method for decreasing data recovery error in a high-speed serial link
Provided are a data recovery apparatus and method for recovering (parallel) data from serial data received via a high-speed serial link with a reduced data recovery error rate. The data recovery...
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7433430 |
Wireless communications device providing enhanced block equalization and related methods
A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The...
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7433392 |
Wireless communications device performing block equalization based upon prior, current and/or future autocorrelation matrix estimates and related methods
A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator...
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7430680 |
System and method to align clock signals
A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer...
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7430259 |
Two-wire chip-to-chip interface
A method for communicating data over a serial interface between a master device and at least one slave device is disclosed. A master device generates a preamble that is attached to a data block for...
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7427885 |
Semiconductor device having a power supply capacitor
In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low...
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7424046 |
Spread spectrum clock signal generation system and method
A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a...
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7421607 |
Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
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7421606 |
DLL phase detection using advanced phase equalization
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
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7421048 |
System and method for multimedia delivery in a wireless environment
A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a...
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7403447 |
Method for stabilizing electronic circuit operation and electronic apparatus using the same
An operation signal generator circuits are provided to continue to operate an object circuit which is not operated unless an operation signal arrives for the purpose of power consumption reduction,...
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7398412 |
Measure controlled delay with duty cycle control
The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the...
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7391255 |
Semiconductor phase adjustment system module
A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a...
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7382844 |
Methods to self-synchronize clocks on multiple chips in a system
A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave...
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7375560 |
Method and apparatus for timing domain crossing
A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The...
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