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5905391 Master-slave delay locked loop for accurate delay or non-periodic signals  
The present invention involves an electrical component interface system. The system includes clocking circuitry to provide a clock signal. A sending component provide a non-periodic strobe signal...
5900754 Delay control circuit  
A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback...
5900751 Automatic frequency control circuit with simplified circuit constitution  
In an automatic frequency control circuit, a circuit constitution thereof is simplified without decreasing performance of demodulation. In the control circuit, a frequency counter counts a number...
5898640 Even bus clock circuit  
An even bus clock circuit generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a given range of processor clock to bus clock ratios...
5896048 Method for determining active/stand-by mode for use in a duplicated system  
An active/stand-by determination method for use in a duplicated system, wherein two elements, one given a priority and the other not given a priority, in the duplicated system operate in an active...
5889421 Device for detecting the locking of an automatic gain control circuit  
The present invention relates to a device for detecting the locking of an automatic gain control circuit, the automatic gain control circuit receiving a signal to be regulated, a check signal and a...
5877640 Device for deriving a clock signal from a synchronizing signal and a videorecorder provided with the device  
A device for deriving a clock signal having a specific frequency, from an electrical signal, for example, a video signal, the device including an input terminal (1) for receiving the synchronizing...
5847596 Internal voltage generator  
An internal voltage generator for a semiconductor device. Whereas a feedback signal is given to maintain a voltage of a predetermined level by a voltage detector in the conventional art, the...
5847588 Programmable multiple CCD clock synthesizer  
The clock synthesizer includes an oscillator section for providing a train of pulses corresponding to the transitions of a master clock signal, a first register coupled to the oscillator for...
5838172 Timing error detecting circuit  
A timing error detecting circuit detects a timing error of a measurement objective circuit by reading an input data in synchronism with rising or falling of a timing signal and outputting a first...
5834957 Implementing asynchronous sequential circuits using synchronous design techniques and modules  
A design method for an asynchronous sequential circuit that employs synchronous design techniques wherein a synchronous sequential circuit is designed to perform a desired function. A terminating...
5835752 PCI interface synchronization  
A PCI interface includes a PCI core that operates at the PCI bus frequency and glue logic which provides an interface to a higher frequency clock domain. The glue logic includes FIFO buffers for...
5831459 Method and system for adjusting a clock signal within electronic circuitry  
A method and system are provided. A clock signal is input and output at first and second nodes of integrated circuitry. The first node is connected through a selected one of a plurality of...
5828250 Differential delay line clock generator with feedback phase control  
An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI,...
5821786 Semiconductor integrated circuit having function for evaluating AC performance  
A semiconductor integrated circuit, having circuit blocks to be evaluated in AC performance, includes a first circuit for inputting a first signal and a second signal generated in the interior of...
5822106 Synchronization of digital systems using optical pulses and mdoulators  
The present invention provides synchronization of logic signals in a digital system using optical pulses generated from optical modulators. In one embodiment of the present invention, electrically...
5818884 High speed synchronous digital data bus system having unterminated data and clock buses  
A high speed synchronous digital bidirectional data bus system is provided and includes an M-bit unterminated data bus, an unterminated standing sine wave clock bus, and a plurality of integrated...
5815015 Synchronization and shutdown circuits and methods in high-speed switching regulator drive circuits  
A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated...
5804991 Zero crossing circuit for a relay  
A relay control circuit that includes a zero cross detector, a latch, and a delay circuit. The zero cross detector circuit detects when the voltage waveform or current waveform on an AC power line...
5798661 Method for continuous waveform synthesis  
A system for synthesizing a waveform that employs combinatorial logic to generate digital data for each of a set of preselected waveform. The system includes circuitry for selecting a sequence of...
5789950 Direct digital synthesizer  
A direct digital synthesizer capable of generating a desired frequency with small circuitry, low power consumption, and no spurious components. It includes an accumulator for accumulating a...
5781587 Clock extraction circuit  
A clock extraction circuit for retiming a ternary data stream derives first and second binary streams corresponding respectively to the positive and negative going portions of the ternary data...
5774507 Synchronous clock controller for digital exchange  
A synchronous clock controller for a digital exchange accommodates installation of a plurality of office line cards. A priority encoder encodes priority information signals respectively provided...
5774001 Method for eliminating multiple output switching timing skews in a source synchronous design  
A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O...
5767709 Synchronous test mode initalization  
The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit...
5764178 Delay characteristic compensation circuit for memory device  
An improved delay characteristic compensation circuit for a memory device which is capable of constantly maintaining the characteristic of the delay path by connecting or disconnecting the delay...
5761253 Method and apparatus for signal transmission  
A method and an apparatus for enabling a data signal to be transmitted stably at high speed over long distances without using thicker cables and without increasing physical quantities of such...
5761097 Logic timing analysis for multiple-clock designs  
A system and method for detecting timing design errors in a design having multiple state devices clocked by multiple clock signals. The design includes at least first and second state devices...
5736905 Synchronizable power supply oscillator  
A dual-multivibrator circuit using a pair of mutually triggering multivibrator sections is connected to operate in a free-running mode when no external synchronization signal is applied to the...
5737637 System for control of data I/O transfer based on cycle count in a semiconductor memory device  
A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by...
5731715 Glitch-free clock enable circuit  
A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock...
5726595 Circuit for coupling an event indication signal across asynchronous time domains  
A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event...
5726596 High-performance, low-skew clocking scheme for single-phase, high-frequency global VLSI processor  
A single-phase clocking scheme for use in a VLSI chip having a plurality of localized logic blocks implemented thereon is presented. The present invention includes a first level global clock buffer...
5723995 Method for eliminating process variation timing skews in a source synchronous design  
A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O...
5703912 Clock-recovery device having cascaded resonance amplifiers  
A circuit for clock recovery from an input signal, particularly an alternating input signal formed from a data signal, the invention calling for a filter/amplifier unit made up of several...
5701105 Timer oscillation circuit with comparator clock control signal synchronized with oscillation signal  
An improved timer oscillation circuit capable of synchronizing an oscillation frequency, which is determined by a time constant of a resistance and a capacitance, to a clock signal, which includes...
5691660 Clock synchronization scheme for fractional multiplication systems  
A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a...
5684841 Clocking converter for asynchronous data  
A clocking converter for asynchronous data capable of performing bit synchronization processes of asynchronous data of different patterns by the same circuit, requiring virtually no change made...
5671257 Symbol timing recovery based on complex sample magnitude  
A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex...
5652536 Non-glitch clock switching circuit  
A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The...
5648993 Method and apparatus for synchronizing modem transmission by controlling a measured phase difference between an internal timing signal and a transmission timing signal  
A transmission synchronizing apparatus and method of a modem, in which a phase difference from a change point of an internal timing signal to a change point of a transmission timing signal is...
5646554 Method and apparatus for selective clocking using a Muller-C element  
The invention relates to the design and operation of local clock control circuits which operate to supply a local clock signal to a controlled block of a digital circuit in response to an enable...
5642065 Zero-voltage switching circuitry, as for use in resonant inverters  
Switching loss in push-pull switching transistors in a resonant inverter or the like, is minimized by assuring the switching of each of the transistors into conduction occurs when the voltage...
5640112 Clock signal distributing system  
A clock signal distributing system supplies clock signals exhibiting extremely matched phases as a standing wave without employing extra signals such as a reference signal and the like other than...
5636165 Apparatus for and method of facilitating proper data transfer between two or more digital memory elements  
An apparatus for and method of ensuring proper transfer of data between two registers. A device driver utilizes a clock signal as an enable input before data is transferred from one register to...
5625310 Signal processing apparatus and displacement detecting apparatus using the same  
A signal processing apparatus is provided for processing first and second periodic analog signals having the same period and having a fixed phase relationship therebetween. The apparatus includes...
5608462 Synchronizing arrangement including a gate circuit and a window circuit for determining the occurrence of output pulses  
A synchronizing arrangement includes a window circuit (WINC1,WINC2) for generating a periodic window signal (LW,RW), and a gate circuit (GC) for supplying a periodic gating pulse (Hp). The gating...
5598113 Fully asynchronous interface with programmable metastability settling time synchronizer  
A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems...
5572550 Decision directed carrier recovery circuit using phase error detector  
A decision directed carrier recovery circuit comprising a demodulator for adjusting a frequency and a phase of an input carrier to demodulate an original signal therefrom, a signal decision unit...
5570054 Method and apparatus for adaptive clock deskewing  
A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors....
Matches 351 - 400 out of 1087 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >