Matches 151 - 200 out of 1085 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6990159 Circuit for generating clock pulses in a communications system  
A circuit arrangement for a communication system for terminating a plurality of interfaces at a common bus and for generating a synchronization clock for synchronizing the bus is provided. In one...
6987823 System and method for aligning internal transmit and receive clocks  
A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock...
6987404 Synchronizer apparatus for synchronizing data from one clock domain to another clock domain  
An improved signal synchronizing circuit for prohibiting signals traveling from a first clock domain operating with a first clock to a second clock domain operating with a second clock when the...
6982575 Clock ratio data synchronizer  
A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a...
6982576 Signal delay compensating circuit  
A signal delay compensating circuit which is a digital circuit includes: a first semiconductor circuit device ( 100 ) having a clock-signal generating circuit ( 1 ) and a data processing circuit (...
6980042 Delay line synchronizer apparatus and method  
A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains...
6977980 Timing synchronization methods and systems for transmit parallel interfaces  
Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit...
6975149 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers  
A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or...
6967510 Time-base implementation for correcting accumulative error with chip frequency scaling  
The present invention provides for supporting an on chip-timer facility and, more particularly, to the generation of a constant time incremental increase while changing core mesh-clock frequency. A...
6966022 System and method for determining integrated circuit logic speed  
An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal...
6958634 Programmable direct interpolating delay locked loop  
Embodiments of the invention provide for a delay locked loop architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be configured for...
6956407 Pre-emphasis circuitry and methods  
Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one...
6956424 Timing of and minimizing external influences on digital signals  
The performance of digital signals depends to a great extent on the frequency. However, the higher the frequency, the shorter the remaining time, in which digital signals can be reliably received...
6950483 Timing misalignment estimation  
Orthogonal frequency division multiplexing (OFDM) receiver embodiments of the invention provide timing misalignment estimation by calculating the intra-baud timing differential. The preferred...
6950956 Integrated circuit with timing adjustment mechanism and method  
An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores...
6946886 Clock-synchronized serial communication device and semiconductor integrated circuit device  
In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a...
6943595 Synchronization circuit  
A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a...
6937076 Clock synchronizing apparatus and method using frequency dependent variable delay  
A clock signal generator providing an output clock signal synchronized with an input clock signal having an input clock frequency including a frequency dependent variable delay line to accommodate...
6933757 Timing method and apparatus for integrated circuit device  
According to one embodiment, a timing circuit ( 300 ) can include a first control circuit ( 302 ), a first clocked circuit ( 304 ), a second clocked circuit ( 306 ), and a second control circuit (...
6933758 Synchronous mirror delay circuit with adjustable locking range  
A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock...
6934349 Phase detector and phase locked loop circuit  
There is disclosed a phase detector and phase locked loop circuit in which a maximum operation frequency is high. The phase detector of the present invention comprises three S-R flip-flops each of...
6927603 Semiconductor integrated circuit having system bus divided in stages  
A semiconductor integrated circuit having a system bus divided into stages and configured to transfer signals, stage elements configured to connect the stages in series and operate in a divided...
6924675 Buffer device  
A buffer device includes a plurality of latch stages which each have a latch device and a multiplexer. At least the multiplexer of the first latch stage on the output side is associated with a...
6922090 Transition signaling circuit and arbitrator using this circuit  
The present invention implements an asynchronous transition signaling circuit which can be applied to a bus arbitrator or the like. The OR gate holds a token (feedback signal S) as long as the...
6911851 Data latch timing adjustment apparatus  
In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to...
6911854 Clock skew tolerant clocking scheme  
A clock skew tolerant clocking scheme addresses both the max-time and min-time problems by using dual transparent pulsed latches operated by complementary phases of the clock signal. According to...
6909417 Shift register and image display apparatus using the same  
A level shifter 13 is provided for each of SR flip flops F 1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a...
6909311 Methods and apparatus for synthesizing a clock signal  
One embodiment of the invention is directed to a method comprising an act of generating a timing signal, wherein at least some rising edges of the timing signal are based on edges of a first delay...
6906554 Pipeline-based circuit with a postponed clock-gating mechanism for reducing power consumption and related driving method thereof  
A pipeline-based circuit with a postponed clock-gating mechanism and related driving method are disclosed for reducing power consumption, and the driving method does not deteriorate processing...
6903582 Integrated circuit timing debug apparatus and method  
A timing debug tool for an IC that enables varying the skew of selected edges of a primary clock signal for a controllable number of clock cycles. The debug tool enables identification, isolation...
6891409 Semiconductor device  
For suppressing increase of terminals in number, a semiconductor device is proposed which includes an input terminal to which an external clock is to be inputted. The semiconductor device further...
6891410 Method and apparatus for determining a processing speed of an integrated circuit  
A method and apparatus for determining a processing speed of an integrated circuit includes a first flip flop having an input port receiving an input signal, an output port providing a flip flop...
6892345 Integrated circuit including duplicated synchronous and asynchronous components  
An IC including duplicated primary components which can be operated microsynchronously has at least one synchronization device for synchronizing asynchronous signals to the primary clock. An...
6891441 Edge synchronized phase-locked loop circuit  
A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an...
6891413 Periodic signal controller  
In a periodic signal controller of the present invention, a first phase difference detection circuit 1 and a first sine-wave signal generation circuit 2 constitute a phase-locked loop for...
6882192 High-speed data buffer  
Disclosed is a high-speed data buffer, wherein a buffer circuit composed of a ring counter is divided into two sampling circuits composed of a rising-edge portion and a falling-edge portion, and...
6879185 Low power clock distribution scheme  
An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an...
6873215 Power down system and method for integrated circuits  
A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator,...
6867626 Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof  
A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first...
6859109 Double-data rate phase-locked-loop with phase aligners to reduce clock skew  
A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other...
6859912 Method and circuit arrangement for clock recovery  
Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at...
6856174 Versatile system for high resolution device calibration  
The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component ( 518 ). The system calibrates the programmable semiconductor component,...
6850101 Single-line synchronizable oscillator circuit  
Single line synchronization enables two or more oscillators to be synchronized with each other by using only a single control line. The synchronization can be accomplished without any external...
6850092 Low latency FIFO circuits for mixed asynchronous and synchronous systems  
A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The...
6842398 Multi-mode synchronous memory device and methods of operating and testing same  
A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input...
6842055 Clock adjustment  
Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback...
6839301 Method and apparatus for improving stability and lock time for synchronous circuits  
Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase...
6839859 Semiconductor integrated circuit having clock synchronous type circuit and clock non-synchronous type circuit  
A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock...
6836165 DLL circuit and method of generating timing signals  
A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied...
6836163 Differential output structure with reduced skew for a single input  
The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output...
Matches 151 - 200 out of 1085 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >